Sun Microelectronics
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17. Grouping Rules and Stalls
MULX, and {U,S}MUL{cc} delay dispatching subsequent instructions for a variable
number of clocks, depending on the value of the rs1 operand. Four bubbles are
inserted when the upper 60 bits of rs1 are zero, or for signed multiplies when the
upper 60 bits of rs1 are one. Otherwise, an additional bubble is inserted each time
the upper 60 bits of rs1 are not zero (or one for signed multiplies) after arithmetic
right shifting rs1 by two bits. This implies a maximum of 18 bubbles for SMUL{cc},
19 bubbles for UMUL{cc}, and 34 bubbles for MULX.
WR{PR} inserts four bubbles after it is dispatched. RDPR from the CANSAVE,
CANRESTORE, CLEANWIN, OTHERWIN, FPRS, and WSTATE registers, and RD
from any register are not dispatchable until four clocks after the instruction reach-
es the first slot of the instruction buffer.
Writes to the TICK, PSTATE, and TL registers and FLUSH{W} instructions cause a
pipeline flush when they reach the W Stage, effectively inserting nine bubbles.
17.5.2 IEU Dependencies
Instructions that have the same destination register (in the same register file) can-
not be grouped together, unless the destination register is %g0. For example:
Instructions that reference the result of an IEU instruction cannot be grouped
with that IEU instruction, unless the result is being stored in %g0. For example:
There are two exceptions to this rule: Integer stores can store the result of an IEU
instruction other than FCMP{LE,NE,GT,EQ}{16,32} and be in the same group. For ex-
ample:
Also, BPicc or Bicc can be grouped with an older instruction that sets the condi-
tion codes. For example:
alu → i6 GECN
1
N
2
N
3
W
load → i6 GECN
1
N
2
N
3
W
alu → i6 GECN
1
N
2
N
3
W
LDX [i6+i1], i8 GECN
1
N
2
N
3
W
alu → r6 GECN
1
N
2
N
3
W
store → r6 GECN
1
N
2
N
3
W
seticc
GECN
1
N
2
N
3
W
BPicc GECN
1
N
2
N
3
W
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