Sun Microelectronics
299
17. Grouping Rules and Stalls
For the preceding two rules, all graphics instructions, FDIVs, FSQRTs, FdTOi,
FsTOx, FiTOd, FxTOs, FsTOd, FdTOs, and FsMULd are considered to be double, even
though a single-precision register is referenced. For example, the following in-
structions can be grouped together:
17.8.2 Floating-Point and Graphics Instruction Latencies
Table 17-1 on page 300 documents the latencies for floating-point and graphics in-
structions. For table entries containing two numbers, premature dispatching oc-
curs when the destination and source precision are different, but both are treated
as double because of a graphics or mixed-precision floating-point instruction. To
avoid the pipe flush overhead, software should explicitly force the use instruction
to be at least the latency number of groups after the source instruction. Mixed
precision bypassing is unlikely to occur with floating-point data. Software sched-
uling is only needed for initializing the PDIST rd register and for graphics instruc-
tions single results used as part of a double-precision graphics source operand, or
vice versa.
The table uses the following abbreviations:
FORs f2, f4, f0 GECN
1
N
2
N
3
W
FANDs f2, f2, f2 GECN
1
N
2
N
3
W
Abbrev Meaning
FGA Graphics A-Class instruction
FGM Graphics M-Class instruction
FPA Floating-point A-Class instruction
FPM Floating-point M-Class instruction
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