Sun Microelectronics
320
UltraSPARC User’s Manual
PIC for accurate timing and not on write-to-read counts. See also Table 10-1, “Ma-
chine State After Reset and in RED_state,” on page 172 for the state of these reg-
isters after reset.
Figure B-1 Performance Control Register (PCR)
S1|S0: Two four-bit fields; each selects a performance instrumentation event
from the list in Section B.4.5, “PCR.S0 and PCR.S1 Encoding,” on page
325. The event selected by S0 is counted in PIC.D0; the event selected by
S1 is counted in PIC.D1.
UT: User_trace. If set, events in non-privileged (user) mode are counted. This
may be set along with PCR.ST to count all selected events.
ST: System_trace. If set, events in privileged (system) mode are counted. This
may be set along with PCR.UT to count all selected events.
PRIV: Privileged. If set, non-privileged access to the PIC will cause a
privileged_action
trap.
Figure B-2 Performance Instrumentation Counters (PIC)
D1|D0: A pair of 32-bit counters; D0 counts the events selected selected by
PCR.S0; D1 counts the events selected selected by PCR.S1.
63 784 0
— S0 PRIV
1
ST
2
UT
3
—
15 14 11
S1
10
—
63 0
D1
3132
D0
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