Sun Microelectronics
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B. Performance Instrumentation
There are also overcounts due to, for example, mispredicted CTIs and dispatched
instructions that are invalidated by traps.
Load_use_RAW [PIC1]
There is a load use in the execute stage and there is a read-after-write hazard on
the oldest outstanding load. This indicates that load data is being delayed by
completion of an earlier store.
Some less common stalls (see Chapter 17, “Grouping Rules and Stalls”) are not
counted by any performance counter, including:
• Stalls associated with WRPR/RDPR and internal ASI loads.
• MEMBAR stalls.
• One cycle stalls due to bad prediction around a change to the Current
Window Pointer (CWP).
B.4.4 Cache Access Statistics
I-, D-, and E-Cache access statistics can be collected. Counts are updated by each
cache access, regardless of whether the access will be used.
IC_ref [PIC0]
I-Cache references. I-Cache references are fetches of up to four instructions from
an aligned block of eight instructions. I-Cache references are generally prefetches
and do not correspond exactly to the instructions executed.
IC_hit [PIC1]
I-Cache hits.
DC_rd [PIC0]
D-Cache read references (including accesses that subsequently trap).
NonD-Cacheable accesses are not counted. Atomic, block load, “internal,” and
“external” bad ASIs, quad precision LDD, and MEMBARs also fall into this class.
Atomic instructions, block loads, “internal” and “external” bad ASIs, quad LDD,
and MEMBARs also fall into this class.
DC_rd_hit [PIC1]
D-Cache read hits are counted in one of two places:
1. When they access the D-Cache tags and do not enter the load buffer
(because it is already empty)
2. When they exit the load buffer (due to a D-Cache miss or a non-
empty load buffer).
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