Sun Microelectronics
19
3. Cache Organization
Instruction fetches bypass the E-Cache when:
• The I-MMU is disabled, or
• The processor is in RED_state, or
• The access is mapped by the I-MMU as physically noncacheable
Data accesses bypass the E-Cache when:
• The D-MMU enable bit (DM) in the LSU_Control_Register is clear, or
• The access is mapped by the D-MMU as nonphysical cacheable (unless
ASI_PHYS_USE_EC is used).
The system must provide a noncacheable, ECC-less scratch memory for use of the
booting code until the MMUs are enabled.
The E-Cache is a unified, write-back, allocating, direct-mapped cache. The
E-Cache always includes the contents of the I-Cache and D-Cache. The E-Cache
size is model dependent (see Table 1-5 on page 10); its line size is 64 bytes.
Block loads and block stores, which load or store a 64-byte line of data from
memory to the floating-point register file, do not allocate into the E-Cache, in or-
der to avoid pollution.
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