Sun Microsystems UltraSPARC-I

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UltraSPARC User’s Manual

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Default Chapter4
- Table of Contents4
- Section I - Introducing Ultrasparc16
1 Ultrasparc Basics18
- Overview18
- Design Philosophy18
- Component Overview20
- Preface24
2 Processor Pipeline26
- Introductions26
- Pipeline Stages27
3 Cache Organization32
- Introduction32
4 Overview of the MMU36
- Introduction36
- Virtual Address Translation36
  - Section II - Going Deeper40
5 Cache and Memory Interactions ........................................................................................ Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | Www.artisantg.com42
- Cache Flushing42
- Memory Accesses and Cacheability44
- Load Buffer54
- Store Buffer55
6 MMU Internal Architecture56
- Introduction56
- Translation Table Entry (TTE)56
- Translation Storage Buffer (TSB)59
- MMU-Related Faults and Traps62
- MMU Operation Summary65
- ASI Value, Context, and Endianness Selection for Translation67
- MMU Behavior During Reset, MMU Disable, and Red_State69
- Compliance with the SPARC-V9 Annex F70
- MMU Internal Registers and ASI Operations70
- MMU Bypass Mode83
- TLB Hardware84
7 Ultrasparc External Interfaces88
- Introduction88
- Overview of Ultrasparc External Interfaces88
- Interaction between E-Cache and UDB91
- SYSADDR Bus Arbitration Protocol99
- Ultrasparc Interconnect Transaction Overview107
- Cache Coherence Protocol109
- Cache Coherent Transactions117
- Non-Cached Data Transactions124
- S_Rto/S_Err126
- S_Req126
- Writeback Issues127
- Interrupts (P_INT_REQ)131
- P_REPLY and S_REPLY132
- Multiple Outstanding Transactions141
- Transaction Set Summary144
- Transaction Sequences146
- Interconnect Packet Formats153
- Writeinvalidate158
8 Address Spaces, Asis, Asrs, and Traps160
- Overview160
- Physical Address Space160
- Ancillary State Registers171
- Other Ultrasparc Registers173
- Supported Traps173
9 Interrupt Handling176
- Interrupt Vectors176
- Interrupt Global Registers178
- Interrupt ASI Registers178
- Software Interrupt (SOFTINT) Register181
10 Reset and Red_State184
- Overview184
- Red_State Trap Vector186
- Machine State after Reset and in Red_State186
11 Error Handling190
- Overview190
- Memory Errors193
- Memory Error Registers194
- Ultrasparc Data Buffer (UDB) Control Register200
- Overwrite Policy200
  - Section III - Ultrasparc and SPARC-V9202
12 Instruction Set Summary204
13 Ultrasparc Extended Instructions210
- Introduction210
- Shutdown210
- Graphics Data Formats211
- Graphics Status Register (GSR)212
- Graphics Instructions213
- Memory Access Instructions240
14 Implementation Dependencies250
- SPARC-V9 General Information250
- SPARC-V9 Integer Operations255
- SPARC-V9 Floating-Point Operations257
- SPARC-V9 Memory-Related Operations262
- Non-SPARC-V9 Extensions264
15 SPARC-V9 Memory Models270
- SPARC-V9 Memory Models ............................................................................................... Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | Www.artisantg.com270
- Supported Memory Models271
- Section IV - Producing Optimized Code274
16 Code Generation Guidelines276
- Hardware / Software Synergy276
- Instruction Stream Issues276
- Data Stream Issues287
17 Grouping Rules and Stalls296
- Introduction296
- General Grouping Rules297
- Instruction Availability298
- Single Group Instructions298
- Integer Execution Unit (IEU) Instructions299
- Control Transfer Instructions302
- Load / Store Instructions305
- Floating-Point and Graphic Instructions310
- Appendixes316
Debug and Diagnostics Support318
- Overview318
- Diagnostics Control and Accesses318
- Dispatch Control Register318
- Floating-Point Control319
- Watchpoint Support319
- Lsu_Control_Register321
- I-Cache Diagnostic Accesses324
- D-Cache Diagnostic Accesses329
- E-Cache Diagnostics Accesses330
Performance Instrumentation334
- Overview334
- Performance Control and Counters334
- PCR/PIC Accesses336
- Performance Instrumentation Counter Events336
Power Management342
- Power-Up343
- C.3 Power-Up343
- Introduction344
- Interface344
- D.1 Introduction344
- Test Access Port (TAP) Controller345
D. IEEE 1149.1 Scan Interface346
- Instruction Register348
- Instructions348
- D.4 Instruction Register348
- Public Test Data Registers350
- Introduction352
- Pin Descriptions352
- E.1 Introduction352
E. Pin and Signal Descriptions354
- Signal Descriptions356
- E.3 Signal Descriptions356
ASI Names360
- Introduction360
  - F.1 Introduction360
  - F. ASI Names362
- Introduction366
- Summary366
- G.1 Introduction366
- References to Model-Specific Information367
G. Differences between Ultrasparc Models368
- Back Matter370
- Glossary372
- Bibliography378

Sun Microsystems UltraSPARC-I - Page 341

Table of Contents