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Sun Microsystems UltraSPARC-I - Page 399

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Sun Microelectronics
384
UltraSPARC User’s Manual P
P_NCBRD_REQ 110, 118, 122, 126, 141
P_NCBWR_REQ 111, 122, 127, 141
P_NCRD_REQ 109, 118 to 120, 122, 126 to 127,
141 to 142
P_NCWR_REQ 110, 120, 122, 127, 141 to 142, 257
P_RAS 118 to 119
P_RASB 153
P_RD*_REQ 111, 122, 126, 128, 144
P_RDD_REQ 96, 104, 108, 122, 134, 141
P_RDO_REQ 96 to 97, 101, 103, 105 to 107, 120,
122, 133 to 134, 137 to 138, 141
P_RDS_REQ 97,102, 106, 122, 131 to132, 135, 137
to 138, 141
P_RDSA_REQ 97, 102, 106, 122, 131, 141, 144
P_REPLY 100 to 101, 111, 117 to 118, 120, 123, 143,
175
class bit 118
definitions 119
encoding 118
MID of requesting UltraSPARC 118
packet format illustrated 118 to 119
timing 123
type 118
P_REPLY (definitions) 119
P_REPLY acknowledgment 92
P_REPLY pins 339
P_REPLY signals 342
P_REPLY transaction 93
P_REQ 116, 119, 142, 153
P_REQ transactioin
interrupt vector access 92
P_REQ transaction 92 to 93
classes 92
noncacheable 92
P_REQ transactions
coherent request for cacheable memory
access 92
P_RERR 118 to 119
P_RTO 120
P_SACK 97, 101, 103, 106 to 109, 115, 118 to 119,
122, 132 to 134, 142
P_SACKD 97, 101,103, 106 to 109, 115, 118 to 120,
122, 137 to 138
P_SNACK 101, 106 to 109, 111 to 112, 115, 118 to
119
P_SNACK transaction 93
P_WRB_REQ 95 to97, 101, 104, 113, 115, 120, 122,
128, 135, 138, 141
P_WRI_REQ 95 to 96, 101, 105 to 106, 122, 127,
141 to 144
PA Data Watchpoint Register 49
illustrated 306
PA Watchpoint Address Register 56
PA, see Physical Page Number (PA) field of TTE
PA_watchpoint
trap 159, 226, 228 to 229, 231, 305
pack instructions 197 to 198, 201
packet formats
interconnect 138
packets
interrupt 76
page number
physical 21
virtual 21
page offset 21
page size
encoding in Translation Table Entry
(TTE) 42
Page Size (Size) field of TTE 42
parity 143
parity bit 143
parity error 40, 175, 178
E-Cache tags 119
on SYSADDR bus 119
Parity Syndrome Error (P_SYND) field of
AFSR 181
partial store ASI 225
partial store instructions 225, 251
to noncacheable addresses 257
Partial Store Order (PSO) memory model 255,
257
partial stores
to noncacheable locations only 92
partitioned add 7
partitioned multiply 7
partitioned multiply instructions 208
PC 360
PC Ancillary State Register (ASR) 156
PCAP, see Processor Capabilities (PCAP) field of
UPA_CONFIG register
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