Sun Microelectronics
386
UltraSPARC User’s Manual P
pixel distance 7
pixel orderings 197
PLL_BYPASSS signal 343
PLLBYPASS signal 342
PM, see Physical Address Data Watchpoint Mask
(PM) field of LSU_Control_Register
PMERGE instruction 206
point-to-point write-invalidate protocol 94
population count (POPC) instruction 240
port_ID field 141
port_ID signal 85 to 86
port_id signal 86
power on
clearing AFSR to avoid false errors 176
power_on_reset
trap 158
power-down mode 196, 253, 327
restart 328
Power-On Reset (POR) 145, 170
Power-on Reset (POR) 175
Power-On Reset (POR) pin 328
Power-On-Reset (POR) 239
Power-on-Reset (POR) 119
PR, see Physical Address Data Watchpoint Read
Enable (PR) field of LSU_Control_Register
precise exception model 7
precise traps 40, 236
Prefech and Dispatch Unit (PDU) 14
Prefetch and Dispatch Unit (PDU) 6,13
illustrated 5
prefetch unit 4
PREFETCHA instruction 248
prefetchable 359
PREQ_DQ, see Number of Entries in P_REQ Data
Read Queue (PREQ_DQ) field of UPA_
CONFIG register
PREQ_DQ, see Number of Entries in P_REQ Data
Read Queue (PREQ_DQ) field of UPA_
PORT_ID register
PREQ_DQ, see Number of Entries in P_REQ Data
Write Queue (PREQ_DQ) field of UPA_
CONFIG register
PREQ_DQ, see Number of Entries in P_REQ Data
Write Queue (PREQ_DQ) field of UPA_
PORT_ID register
Primary Context Register 57
PRIV, see Privileged (PRIV) field of PCR register
Privilege (PRIV) field of AFSR 177
privilege (PRIV) field of PSTATE register 180
privilege violation 60
privileged 47, 360
Privileged (P) field of TTE 44
Privileged (PR) field of SFSR register 59
Privileged (PRIV) field of PCR register 157, 319
to 320
Privileged (PRIV) field of PSTATE register 34, 44,
48 to 49, 256, 359 to 360, 362
Privileged Access (PRIV) field of AFSR 181
privileged mode 360
privileged_action
trap 34, 47, 49, 51, 156 to 157, 159,
164 to 166, 239, 256, 319
privileged_opcode
trap 157, 159, 166 to 167, 196,
249, 304, 319
privilege-error field (PRIV) of AFSR 180
Processor Capabilities (PCAP) field of UPA_
CONFIG register 156
Processor Configuration (PCON) field of UPA_
CONFIG register 155
processor front end components 261
processor interrupt level (PIL) 167
Processor Interrupt Level (PIL) field of PSTATE
register 250
processor interrupt level (PIL) field of PSTATE
register 167
processor memory model 233
processor-to-UPA frequency ratio 292
program counter 360
program order 32
protection violation 49
protocol
cache coherence 94
PSO 295
mode 30, 32
PSO memory model 249
PSTATE 232
PSTATE global register selection encodings 252
PSTATE Register 251, 253, 285
PW, see Physical Address Data Watchpoint Write
Enable (PW) field of LSU_Control_Register
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