Sun Microelectronics
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6. MMU Internal Architecture
No hardware TSB indexing support is provided for the 512 Kb and 4 Mb page
TTEs. Since the TSB is entirely software managed, however, the operating system
may choose to place these larger page TTEs in the TSB by forming the appropri-
ate pointers. In addition, simple modifications to the 8 Kb and 64 Kb index point-
ers provided by the hardware allow formation of an M-way set-associative TSB,
multiple TSBs per page size, and multiple TSBs per process.
The TSB exists as a normal data structure in memory, and therefore may be
cached. Indeed, the speed of the TLB miss handler relies on the TSB accesses hit-
ting the level-2 cache at a substantial rate. This policy may result in some con-
flicts with normal instruction and data accesses, but the dynamic sharing of the
level-2 cache resource should provide a better overall solution than that provided
by a fixed partitioning.
Figure 6-2 shows both the common and shared TSB organization. The constant N
is determined by the Size field in the TSB register; it may range from 512 to 64K.
Figure 6-2 TSB Organization
6.3.1 Hardware Support for TSB Access
The MMU hardware provides services to allow the TLB miss handler to efficient-
ly reload a missing TLB entry for an 8 Kb or 64 Kb page. These services include:
• Formation of TSB Pointers based on the missing virtual address.
• Formation of the TTE Tag Target used for the TSB tag comparison.
• Efficient atomic write of a TLB entry with a single store ASI operation.
• Alternate globals on MMU-signalled traps.
Tag1 (8 bytes) Data1 (8 bytes)
0000
16
0008
16
Tag
N
(8 bytes) Data
N
(8 bytes)
N
Lines in Common TSB
Tag1 (8 bytes) Data1 (8 bytes)
Tag
N
(8 bytes) Data
N
(8 bytes)
2
N
Lines in Split TSB
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