Sun Microelectronics
74
UltraSPARC User’s Manual
The UltraSPARC Data Buffer isolates UltraSPARC and its E-Cache from the main
system data bus, so the interface can operate at processor speed (reduced load-
ing). The UDB also provides overlapping between system transactions and local
E-Cache transactions, even when the latter needs to use part of the data buffer.
UltraSPARC includes the logic to control the UDB; this provides fast data trans-
fers to and from UltraSPARC or to and from the E-Cache and the system. A sep-
arate address bus and separate control signals support system transactions.
Figure 7-1 Main UltraSPARC Interfaces
UltraSPARC is both an interconnect master and an interconnect slave.
• As an interconnect master, UltraSPARC issues read/write transactions to the
interconnect using part of the transaction set (Section 7.5 ). As a master, it also
has physically addressed coherent caches, which participate in the cache
coherence protocol, and respond to the interconnect for copyback and
invalidation requests.
E-Cache Tag
E-Cache Tag Data
E-Cache Data
Byte Write Enable
E-Cache Data Bus
System Data Bus
System Address
P_REPLY
S_REPLY
Clocks,
Reset, etc.
Observability,
JTAG, etc.
15
E$TagAddrBits
22+3 state + 4 parity
16
128 + 16 parity
128 +16 ECC
E-Cache Tag
RAM
E-Cache Data
RAM
4
5
UDB
Control
5
S
Y
S
T
E
M
35+parity
4
Arbitration
6
UltraSPARC
Address
Address
UltraSPARC
Data
Buffer
E$DataAddrBits
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