VIPA CPU 21 Series User Manual

Manual VIPA CPU 21x Chapter 4 Deployment of the CPU 21x-2BT10 with TCP/IP
HB103E - Rev. 05/45 4-49
For the processing of connection commands at the PLC, a PLC user
program is necessary in the concerning CPU. For this only the handling
blocks AG_SEND (FC5) and AG_RECV (FC6) are used. By including this
blocks into the cycle block OB1 with the parameters ID and LADDR you
may cyclically send and receive data.
The two FCs are part of the VIPA library that is included in the consignment
of the CPU as CD.
Via the cycle OB OB1 the sending and receiving of the data is controlled.
The OB1 that you may transfer into both CPUs has the following structure:
UN T 1 // Timer 1 triggered sending
L S5T#1S // Send initiation every 1 sec
SV T 1
S M 10.0 // Init bit memory
CALL "AG_SEND"
ACT :=M10.0 // Init bit memory
ID :=1 // Connection number
LADDR :=W#16#110 // Module address
SEND :=P#DB11.DBX0.0 BYTE 100 // Send buffer area DB11
LEN :=32 // send 32 Byte (16 Words) from DB11
DONE :=M10.1
ERROR :=#Senderror // Temporary error bit memory
STATUS:=MW12 // Order res. connection state
U M 10.1 // Send ready?
SPBN nDon
U M 10.1 // Send ready?
R M 10.0 // Set back init
U #Senderror // At send error
SPB nDon // Don’t raise send counter
L DB11.DBW 0 // Send counter in user data (DBW0)
L 1 // increment for 1 and
+I // store again in send buffer
T DB11.DBW 0
nDon: NOP 0 // Send not ready yet
// Cyclic call of the receive block
CALL "AG_RECV"
ID :=1 // Connection number
LADDR :=W#16#110 // Module address
RECV :=P#DB12.DBX100.0 BYTE 32 //Receive buffer
NDR :=#Newdata // NewDataReceived?
ERROR :=M0.1 // RecError
STATUS:=MW2 // Order res. connection state
LEN :=#Reclen // Really received length
NOP 0 // Reclen can be at IsoOnTCP < 32
U #Newdata // when new data received
ZV Z 1 // Increment Receive counter Counter1
L Z 1 // reset counter 1 at overflow
L 999
==I
R Z 1
PLC user program
OB 1
Cycle

VIPA CPU 21 Series Specifications

General

Brand	VIPA
Model	CPU 21 Series
Category	Control Unit
Language	English