Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 138
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_DP_RVALID
M_AXI_DP I
Slave Read valid
M_AXI_DP_RREADY
M_AXI_DP O
Master Read ready
M_AXI_IP_AWID
M_AXI_IP O
Master Write address ID
M_AXI_IP_AWADDR
M_AXI_IP O
Master Write address
M_AXI_IP_AWLEN
M_AXI_IP O
Master Burst length
M_AXI_IP_AWSIZE
M_AXI_IP O
Master Burst size
M_AXI_IP_AWBURST
M_AXI_IP O
Master Burst type
M_AXI_IP_AWLOCK
M_AXI_IP O
Master Lock type
M_AXI_IP_AWCACHE
M_AXI_IP O
Master Cache type
M_AXI_IP_AWPROT
M_AXI_IP O
Master Protection type
M_AXI_IP_AWQOS
M_AXI_IP O
Master Quality of Service
M_AXI_IP_AWVALID
M_AXI_IP O
Master Write address valid
M_AXI_IP_AWREADY
M_AXI_IP I
Slave Write address ready
M_AXI_IP_WDATA
M_AXI_IP O
Master Write data
M_AXI_IP_WSTRB
M_AXI_IP O
Master Write strobes
M_AXI_IP_WLAST
M_AXI_IP O
Master Write last
M_AXI_IP_WVALID
M_AXI_IP O
Master Write valid
M_AXI_IP_WREADY
M_AXI_IP I
Slave Write ready
M_AXI_IP_BID
M_AXI_IP I
Slave Response ID
M_AXI_IP_BRESP
M_AXI_IP I
Slave Write response
M_AXI_IP_BVALID
M_AXI_IP I
Slave Write response valid
M_AXI_IP_BREADY
M_AXI_IP O
Master Response ready
M_AXI_IP_ARID
M_AXI_IP O
Master Read address ID
M_AXI_IP_ARADDR
M_AXI_IP O
Master Read address
M_AXI_IP_ARLEN
M_AXI_IP O
Master Burst length
M_AXI_IP_ARSIZE
M_AXI_IP O
Master Burst size
M_AXI_IP_ARBURST
M_AXI_IP O
Master Burst type
M_AXI_IP_ARLOCK
M_AXI_IP O
Master Lock type
M_AXI_IP_ARCACHE
M_AXI_IP O
Master Cache type
M_AXI_IP_ARPROT
M_AXI_IP O
Master Protection type
M_AXI_IP_ARQOS
M_AXI_IP O
Master Quality of Service
M_AXI_IP_ARVALID
M_AXI_IP O
Master Read address valid
M_AXI_IP_ARREADY
M_AXI_IP I
Slave Read address ready
M_AXI_IP_RID
M_AXI_IP I
Slave Read ID tag
M_AXI_IP_RDATA
M_AXI_IP I
Slave Read data
Table 3-1: Summary of MicroBlaze Core I/O (Cont’d)
Signal Interface I/O Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module