Xilinx MicroBlaze - Page 138

MicroBlaze Processor Reference Guide 139
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_IP_RRESP
M_AXI_IP I
Slave Read response
M_AXI_IP_RLAST
M_AXI_IP I
Slave Read last
M_AXI_IP_RVALID
M_AXI_IP I
Slave Read valid
M_AXI_IP_RREADY
M_AXI_IP O
Master Read ready
M_AXI_DC_AWADDR
M_AXI_DC O
Master Write address
M_AXI_DC_AWLEN
M_AXI_DC O
Master Burst length
M_AXI_DC_AWSIZE
M_AXI_DC O
Master Burst size
M_AXI_DC_AWBURST
M_AXI_DC O
Master Burst type
M_AXI_DC_AWLOCK
M_AXI_DC O
Master Lock type
M_AXI_DC_AWCACHE
M_AXI_DC O
Master Cache type
M_AXI_DC_AWPROT
M_AXI_DC O
Master Protection type
M_AXI_DC_AWQOS
M_AXI_DC O
Master Quality of Service
M_AXI_DC_AWVALID
M_AXI_DC O
Master Write address valid
M_AXI_DC_AWREADY
M_AXI_DC I
Slave Write address ready
M_AXI_DC_AWUSER
M_AXI_DC O
Master Write address user signals
M_AXI_DC_AWDOMAIN
M_ACE_DC O
Master Write address domain
M_AXI_DC_AWSNOOP
M_ACE_DC O
Master Write address snoop
M_AXI_DC_AWBAR
M_ACE_DC O
Master Write address barrier
M_AXI_DC_WDATA
M_AXI_DC O
Master Write data
M_AXI_DC_WSTRB
M_AXI_DC O
Master Write strobes
M_AXI_DC_WLAST
M_AXI_DC O
Master Write last
M_AXI_DC_WVALID
M_AXI_DC O
Master Write valid
M_AXI_DC_WREADY
M_AXI_DC I
Slave Write ready
M_AXI_DC_WUSER
M_AXI_DC O
Master Write user signals
M_AXI_DC_BRESP
M_AXI_DC I
Slave Write response
M_AXI_DC_BID
M_AXI_DC I
Slave Response ID
M_AXI_DC_BVALID
M_AXI_DC I
Slave Write response valid
M_AXI_DC_BREADY
M_AXI_DC O
Master Response ready
M_AXI_DC_BUSER
M_AXI_DC I
Slave Write response user signals
M_AXI_DC_WACK
M_ACE_DC O
Slave Write acknowledge
M_AXI_DC_ARID
M_AXI_DC O
Master Read address ID
M_AXI_DC_ARADDR
M_AXI_DC O
Master Read address
M_AXI_DC_ARLEN
M_AXI_DC O
Master Burst length
M_AXI_DC_ARSIZE
M_AXI_DC O
Master Burst size
M_AXI_DC_ARBURST
M_AXI_DC O
Master Burst type
Table 3-1: Summary of MicroBlaze Core I/O (Cont’d)
Signal Interface I/O Description
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