Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 140
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_DC_ARLOCK
M_AXI_DC O
Master Lock type
M_AXI_DC_ARCACHE
M_AXI_DC O
Master Cache type
M_AXI_DC_ARPROT
M_AXI_DC O
Master Protection type
M_AXI_DC_ARQOS
M_AXI_DC O
Master Quality of Service
M_AXI_DC_ARVALID
M_AXI_DC O
Master Read address valid
M_AXI_DC_ARREADY
M_AXI_DC I
Slave Read address ready
M_AXI_DC_ARUSER
M_AXI_DC O
Master Read address user signals
M_AXI_DC_ARDOMAIN
M_ACE_DC O
Master Read address domain
M_AXI_DC_ARSNOOP
M_ACE_DC O
Master Read address snoop
M_AXI_DC_ARBAR
M_ACE_DC O
Master Read address barrier
M_AXI_DC_RID
M_AXI_DC I
Slave Read ID tag
M_AXI_DC_RDATA
M_AXI_DC I
Slave Read data
M_AXI_DC_RRESP
M_AXI_DC I
Slave Read response
M_AXI_DC_RLAST
M_AXI_DC I
Slave Read last
M_AXI_DC_RVALID
M_AXI_DC I
Slave Read valid
M_AXI_DC_RREADY
M_AXI_DC O
Master Read ready
M_AXI_DC_RUSER
M_AXI_DC I
Slave Read user signals
M_AXI_DC_RACK
M_ACE_DC O
Master Read acknowledge
M_AXI_DC_ACVALID
M_ACE_DC I
Slave Snoop address valid
M_AXI_DC_ACADDR
M_ACE_DC I
Slave Snoop address
M_AXI_DC_ACSNOOP
M_ACE_DC I
Slave Snoop address snoop
M_AXI_DC_ACPROT
M_ACE_DC I
Slave Snoop address protection type
M_AXI_DC_ACREADY
M_ACE_DC O
Master Snoop ready
M_AXI_DC_CRREADY
M_ACE_DC I
Slave Snoop response ready
M_AXI_DC_CRVALID
M_ACE_DC O
Master Snoop response valid
M_AXI_DC_CRRESP
M_ACE_DC O
Master Snoop response
M_AXI_DC_CDVALID
M_ACE_DC O
Master Snoop data valid
M_AXI_DC_CDREADY
M_ACE_DC I
Slave Snoop data ready
M_AXI_DC_CDDATA
M_ACE_DC O
Master Snoop data
M_AXI_DC_CDLAST
M_ACE_DC O
Master Snoop data last
M_AXI_IC_AWID
M_AXI_IC O
Master Write address ID
M_AXI_IC_AWADDR
M_AXI_IC O
Master Write address
M_AXI_IC_AWLEN
M_AXI_IC O
Master Burst length
M_AXI_IC_AWSIZE
M_AXI_IC O
Master Burst size
M_AXI_IC_AWBURST
M_AXI_IC O
Master Burst type
Table 3-1: Summary of MicroBlaze Core I/O (Cont’d)
Signal Interface I/O Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module