Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 141
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_IC_AWLOCK
M_AXI_IC O
Master Lock type
M_AXI_IC_AWCACHE
M_AXI_IC O
Master Cache type
M_AXI_IC_AWPROT
M_AXI_IC O
Master Protection type
M_AXI_IC_AWQOS
M_AXI_IC O
Master Quality of Service
M_AXI_IC_AWVALID
M_AXI_IC O
Master Write address valid
M_AXI_IC_AWREADY
M_AXI_IC I
Slave Write address ready
M_AXI_IC_AWUSER
M_AXI_IC O
Master Write address user signals
M_AXI_IC_AWDOMAIN
M_ACE_IC O
Master Write address domain
M_AXI_IC_AWSNOOP
M_ACE_IC O
Master Write address snoop
M_AXI_IC_AWBAR
M_ACE_IC O
Master Write address barrier
M_AXI_IC_WDATA
M_AXI_IC O
Master Write data
M_AXI_IC_WSTRB
M_AXI_IC O
Master Write strobes
M_AXI_IC_WLAST
M_AXI_IC O
Master Write last
M_AXI_IC_WVALID
M_AXI_IC O
Master Write valid
M_AXI_IC_WREADY
M_AXI_IC I
Slave Write ready
M_AXI_IC_WUSER
M_AXI_IC O
Master Write user signals
M_AXI_IC_BID
M_AXI_IC I
Slave Response ID
M_AXI_IC_BRESP
M_AXI_IC I
Slave Write response
M_AXI_IC_BVALID
M_AXI_IC I
Slave Write response valid
M_AXI_IC_BREADY
M_AXI_IC O
Master Response ready
M_AXI_IC_BUSER
M_AXI_IC I
Slave Write response user signals
M_AXI_IC_WACK
M_ACE_IC O
Slave Write acknowledge
M_AXI_IC_ARID
M_AXI_IC O
Master Read address ID
M_AXI_IC_ARADDR
M_AXI_IC O
Master Read address
M_AXI_IC_ARLEN
M_AXI_IC O
Master Burst length
M_AXI_IC_ARSIZE
M_AXI_IC O
Master Burst size
M_AXI_IC_ARBURST
M_AXI_IC O
Master Burst type
M_AXI_IC_ARLOCK
M_AXI_IC O
Master Lock type
M_AXI_IC_ARCACHE
M_AXI_IC O
Master Cache type
M_AXI_IC_ARPROT
M_AXI_IC O
Master Protection type
M_AXI_IC_ARQOS
M_AXI_IC O
Master Quality of Service
M_AXI_IC_ARVALID
M_AXI_IC O
Master Read address valid
M_AXI_IC_ARREADY
M_AXI_IC I
Slave Read address ready
M_AXI_IC_ARUSER
M_AXI_IC O
Master Read address user signals
M_AXI_IC_ARDOMAIN
M_ACE_IC O
Master Read address domain
Table 3-1: Summary of MicroBlaze Core I/O (Cont’d)
Signal Interface I/O Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module