Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 142
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_IC_ARSNOOP
M_ACE_IC O
Master Read address snoop
M_AXI_IC_ARBAR
M_ACE_IC O
Master Read address barrier
M_AXI_IC_RID
M_AXI_IC I
Slave Read ID tag
M_AXI_IC_RDATA
M_AXI_IC I
Slave Read data
M_AXI_IC_RRESP
M_AXI_IC I
Slave Read response
M_AXI_IC_RLAST
M_AXI_IC I
Slave Read last
M_AXI_IC_RVALID
M_AXI_IC I
Slave Read valid
M_AXI_IC_RREADY
M_AXI_IC O
Master Read ready
M_AXI_IC_RUSER
M_AXI_IC I
Slave Read user signals
M_AXI_IC_RACK
M_ACE_IC O
Master Read acknowledge
M_AXI_IC_ACVALID
M_ACE_IC I
Slave Snoop address valid
M_AXI_IC_ACADDR
M_ACE_IC I
Slave Snoop address
M_AXI_IC_ACSNOOP
M_ACE_IC I
Slave Snoop address snoop
M_AXI_IC_ACPROT
M_ACE_IC I
Slave Snoop address protection type
M_AXI_IC_ACREADY
M_ACE_IC O
Master Snoop ready
M_AXI_IC_CRREADY
M_ACE_IC I
Slave Snoop response ready
M_AXI_IC_CRVALID
M_ACE_IC O
Master Snoop response valid
M_AXI_IC_CRRESP
M_ACE_IC O
Master Snoop response
M_AXI_IC_CDVALID
M_ACE_IC O
Master Snoop data valid
M_AXI_IC_CDREADY
M_ACE_IC I
Slave Snoop data ready
M_AXI_IC_CDDATA
M_ACE_IC O
Master Snoop data
M_AXI_IC_CDLAST
M_ACE_IC O
Master Snoop data last
Data_Addr[0:N-1]
DLMB O
Data interface LMB address bus, N = 32 - 64
Byte_Enable[0:3]
DLMB O
Data interface LMB byte enables
Data_Write[0:31]
DLMB O
Data interface LMB write data bus
D_AS
DLMB O
Data interface LMB address strobe
Read_Strobe
DLMB O
Data interface LMB read strobe
Write_Strobe
DLMB O
Data interface LMB write strobe
Data_Read[0:31]
DLMB I
Data interface LMB read data bus
DReady
DLMB I
Data interface LMB data ready
DWait
DLMB I
Data interface LMB data wait
DCE
DLMB I
Data interface LMB correctable error
DUE
DLMB I
Data interface LMB uncorrectable error
Instr_Addr[0:31]
ILMB O
Instruction interface LMB address bus
I_AS
ILMB O
Instruction interface LMB address strobe
Table 3-1: Summary of MicroBlaze Core I/O (Cont’d)
Signal Interface I/O Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module