Xilinx MicroBlaze - Page 198

MicroBlaze Processor Reference Guide 199
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
and
Logical AND
and
rD, rA, rB
1 0 0 0 0 1 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
The contents of register rA are ANDed with the contents of register rB; the result is placed into register
rD.
Pseudocode
(rD) ← (rA) ∧ (rB)
Registers Altered
•rD
Latency
1 cycle
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