Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 198
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
addi
Arithmetic Add Immediate
addi
rD, rA, IMM
Add Immediate
addic
rD, rA, IMM
Add Immediate with Carry
addik
rD, rA, IMM
Add Immediate and Keep Carry
addikc
rD, rA, IMM
Add Immediate with Carry and Keep Carry
0 0 1 K C 0 rD rA
IMM
0 6 11 16
31
Description
The sum of the contents of registers rA and the value in the IMM field, sign-extended to 32 bits, is
placed into register rD. Bit 3 of the instruction (labeled as K in the figure) is set to one for the
mnemonic addik. Bit 4 of the instruction (labeled as C in the figure) is set to one for the mnemonic
addic. Both bits are set to one for the mnemonic addikc.
When an addi instruction has bit 3 set (addik, addikc), the carry flag will keep its previous value
regardless of the outcome of the execution of the instruction. If bit 3 is cleared (addi, addic), then the
carry flag will be affected by the execution of the instruction.
When bit 4 of the instruction is set to one (addic, addikc), the content of the carry flag (MSR[C]) affects
the execution of the instruction. When bit 4 is cleared (addi, addik), the content of the carry flag does
not affect the execution of the instruction (providing a normal addition).
Pseudocode
if C = 0 then
(rD) ← (rA) + sext(IMM)
else
(rD)
← (rA) + sext(IMM) + MSR[C]
if K = 0 then
MSR[C]
← CarryOut
Registers Altered
•rD
•MSR[C]
Latency
1 cycle
Notes
The C bit in the instruction opcode is not the same as the carry bit in the MSR.
By default, Type B Instructions take the 16-bit IMM field value and sign extend it to 32 bits to use as
the immediate operand. This behavior can be overridden by preceding the Type B instruction with an
imm instruction. See the instruction
“imm,” page 241 for details on using 32-bit immediate values.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module