MicroBlaze Processor Reference Guide 209
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
ble
Branch if Less or Equal
ble
rA, rB
Branch if Less or Equal
bled
rA, rB
Branch if Less or Equal with Delay
1 0 0 1 1 1 D 0 0 1 1 rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
Branch if rA is less or equal to 0, to the instruction located in the offset value of rB. The target of the
branch will be the instruction at address PC + rB.
The mnemonic bled will set the D bit. The D bit determines whether there is a branch delay slot or not.
If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is,
in the branch delay slot) is allowed to complete execution before executing the target instruction. If
the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the
branch is the target instruction.
Pseudocode
If rA <= 0 then
PC ← PC + rB
else
PC
← PC + 4
if D = 1 then
allow following instruction to complete execution
Registers Altered
•PC
Latency
• 1 cycle (if branch is not taken)
• 2 cycles (if branch is taken and the D bit is set)
• 3 cycles (if branch is taken and the D bit is not set)
Note
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
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