Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 37
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Translation Look-Aside Buffer Low Register (TLBLO)
The Translation Look-Aside Buffer Low Register is used to access MMU Unified Translation
Look-Aside Buffer (UTLB) entries. It is controlled by the
C_USE_MMU configuration option on
MicroBlaze. The register is only implemented if
C_USE_MMU is greater than 1 (User Mode),
and
C_AREA_OPTIMIZED is set to 0 (Performance) or 2 (Frequency). When accessed with the
MFS and MTS instructions, the TLBLO is specified by setting Sa = 0x1003.
When reading or writing TLBLO, the UTLB entry indexed by the TLBX register is accessed.
The register is readable according to the memory management special registers parameter
C_MMU_TLB_ACCESS.
When the MMU Physical Address Extension (PAE) is enabled (parameters C_USE_MMU = 3
and
C_ADDR_SIZE > 32), the 32 least significant bits of TLBLO are accessed with the MFS
and MTS instructions, and the most significant bits with the MFSE and MTSE instruction.
When writing the register with PAE enabled, the most significant bits must be written first.
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBLO entries).
Note: The UTLB is not reset by the external reset inputs: Reset and Debug_Rst. This means that
the entire UTLB must be initialized after reset, to avoid any stale data.
The following figure illustrates the TLBLO register and Table 2-20 provides bit descriptions
and reset values. When PAE is enabled the RPN field of the register is extended according
to the
C_ADDR_SIZE parameter up to 54 bits to be able to hold up to a 64-bit physical
address.
Table 2-19: Zone Protection Register (ZPR)
Bits Name Description Reset Value
0:1
2:3
...
30:31
ZP0
ZP1
...
ZP15
Zone Protect
User mode (MSR[UM] = 1):
00 = Override V in TLB entry. No access to the page is allowed
01 = No override. Use V, WR and EX from TLB entry
10 = No override. Use V, WR and EX from TLB entry
11 = Override WR and EX in TLB entry. Access the page as writable
and executable
Privileged mode (MSR[UM] = 0):
00 = No override. Use V, WR and EX from TLB entry
01 = No override. Use V, WR and EX from TLB entry
10 = Override WR and EX in TLB entry. Access the page as writable
and executable
11 = Override WR and EX in TLB entry. Access the page as writable
and executable
Read/Write
0x00000000
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module