Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 36
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
PID is also used when accessing a TLB entry:
• When writing Translation Look-Aside Buffer High (TLBHI) the value of PID is stored in
the TID field of the TLB entry
• When reading TLBHI and MSR[UM] is not set, the value in the TID field is stored in PID
The following figure illustrates the PID register and Table 2-18 provides bit descriptions and
reset values.
Zone Protection Register (ZPR)
The Zone Protection Register is used to override MMU memory protection defined in TLB
entries. It is controlled by the
C_USE_MMU configuration option on MicroBlaze. The register
is only implemented if
C_USE_MMU is greater than 1 (User Mode), C_AREA_OPTIMIZED is set
to 0 (Performance) or 2 (Frequency), and if the number of specified memory protection
zones is greater than zero (
C_MMU_ZONES > 0). The implemented register bits depend on the
number of specified memory protection zones (
C_MMU_ZONES). When accessed with the
MFS and MTS instructions, the ZPR is specified by setting Sa = 0x1001. The register is
accessible according to the memory management special registers parameter
C_MMU_TLB_ACCESS.
The following figure illustrates the ZPR register and Table 2-19 provides bit descriptions
and reset values.
X-Ref Target - Figure 2-12
Figure 2-12: PID
31
24
PID
RESERVED
0
X19749-091317
Table 2-18: Process Identifier Register (PID)
Bits Name Description Reset Value
0:23 Reserved
24:31 PID Used to uniquely identify a software process during MMU
address translation.
Read/Write
0x00
X-Ref Target - Figure 2-13
Figure 2-13: ZPR
30
ZP15
28
ZP14
26
ZP13
24
ZP12
22
ZP11
20
ZP10
18
ZP9
16
ZP8
14
ZP7
12
ZP6
10
ZP5
8
ZP4
6
ZP3
4
ZP2
2
ZP1
0
ZP0
X19750-091317
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module