Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 35
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Stack High Register (SHR)
The Stack High Register stores the stack high limit use to detect stack underflow. When the
address of a load or store instruction using the stack pointer (register R1) as rA is greater
than the Stack High Register, a stack underflow occurs, causing a Stack Protection Violation
exception if exceptions are enabled in MSR.
When read with the MFS instruction, the SHR is specified by setting Sa = 0x0802. The
following figure illustrates the SHR register and
Table 2-17 provides bit descriptions and
reset values.
Note: The register is only implemented if stack protection is enabled by setting the parameter
C_USE_STACK_PROTECTION to 1. If stack protection is not implemented, writing to the register has
no effect.
Note: Stack protection is not available when the MMU is enabled (C_USE_MMU > 0). With the MMU
page-based memory protection is provided through the UTLB instead.
Process Identifier Register (PID)
The Process Identifier Register is used to uniquely identify a software process during MMU
address translation. It is controlled by the
C_USE_MMU configuration option on MicroBlaze.
The register is only implemented if
C_USE_MMU is greater than 1 (User Mode) and
C_AREA_OPTIMIZED is set to 0 (Performance) or 2 (Frequency).
When accessed with the MFS and MTS instructions, the PID is specified by setting Sa =
0x1000. The register is accessible according to the memory management special registers
parameter
C_MMU_TLB_ACCESS.
Table 2-16: Stack Low Register (SLR)
Bits Name Description Reset Value
0:31 SLR Stack Low Register 0x00000000
X-Ref Target - Figure 2-11
Figure 2-11: SHR
SHR
310
X19748-082517
Table 2-17: Stack High Register (SHR)
Bits Name Description Reset Value
0:31 SHR Stack High Register 0xFFFFFFFF
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module