Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 42
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Translation Look-Aside Buffer Search Index Register (TLBSX)
The Translation Look-Aside Buffer Search Index Register (TLBSX) is used to search for a
virtual page number in the Unified Translation Look-Aside Buffer (UTLB). It is controlled by
the
C_USE_MMU configuration option on the MicroBlaze processor.
The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and
C_AREA_OPTIMIZED is set to 0 (Performance) or 2 (Frequency).
When written with the MTS instruction, the TLBSX is specified by setting Sa = 0x1005. The
following figure illustrates the TLBSX register and
Table 2-23 provides bit descriptions and
reset values.
Processor Version Register (PVR)
The Processor Version Register is controlled by the C_PVR configuration option on
MicroBlaze.
• When C_PVR is set to 0 (None) the processor does not implement any PVR and
MSR[PVR]=0.
• When
C_PVR is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and
if set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented.
When read with the MFS or MFSE instruction the PVR is specified by setting Sa = 0x200x,
with x being the register number between 0x0 and 0xB.
X-Ref Target - Figure 2-17
Figure 2-17: TLBSX
31
22
Reserved
VPN
0
X19754-082517
Table 2-23: Translation Look-Aside Buffer Index Search Register (TLBSX)
Bits Name Description Reset Value
0:21 VPN Virtual Page Number
This field represents the page number portion of the virtual memory
address. It is compared with the page number portion of the virtual
memory address under the control of the SIZE field, in each of the
Translation Look-Aside Buffer entries that have the V bit set to 1.
If the virtual page number is found, the TLBX register is written with
the index of the TLB entry and the MISS bit in TLBX is cleared to 0. If
the virtual page number is not found in any of the TLB entries, the
MISS bit in the TLBX register is set to 1.
Write Only
22:31 Reserved
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module