MicroBlaze Processor Reference Guide 41
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Translation Look-Aside Buffer Index Register (TLBX)
The Translation Look-Aside Buffer Index Register is used as an index to the Unified
Translation Look-Aside Buffer (UTLB) when accessing the TLBLO and TLBHI registers. It is
controlled by the
C_USE_MMU configuration option on MicroBlaze. The register is only
implemented if
C_USE_MMU is greater than 1 (User Mode), and C_AREA_OPTIMIZED is set to
0 (Performance) or 2 (Frequency). When accessed with the MFS and MTS instructions, the
TLBX is specified by setting
Sa = 0x1002.
The following figure illustrates the TLBX register and Table 2-22 provides bit descriptions
and reset values.
X-Ref Target - Figure 2-16
Figure 2-16: TLBX
31
26
INDEX
ReservedMISS
0
X19753-082517
Table 2-22: Translation Look-Aside Buffer Index Register (TLBX)
Bits Name Description Reset Value
0 MISS TLB Miss
This bit is cleared to 0 when the TLBSX register is written with a
virtual address, and the virtual address is found in a TLB entry.
The bit is set to 1 if the virtual address is not found. It is also cleared
when the TLBX register itself is written.
Read Only
Can be read if the memory management special registers
parameter
C_MMU_TLB_ACCESS > 0 (MINIMAL).
0
1:25 Reserved
26:31 INDEX TLB Index
This field is used to index the Translation Look-Aside Buffer entry
accessed by the TLBLO and TLBHI registers. The field is updated
with a TLB index when the TLBSX register is written with a virtual
address, and the virtual address is found in the corresponding TLB
entry.
Read/Write
Can be read and written if the memory management special
registers parameter
C_MMU_TLB_ACCESS > 0 (MINIMAL).
000000
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