Xilinx ZCU106 User Manual

ZCU106 Board User Guide 95
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
SMA
One MGT in bank 225 is provided on TX and RX SMA connector pairs. Available MGT clocks
include the FMC defined GBT clock 0 for HPC1 and a jitter attenuated recovered clock from
a Si5328. Table 3-37 through Table 3-41 list the five GTH transceiver bank (223-227)
connections.
Table 3-37: GTH Transceiver Bank 223 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
AN6 MGTHTXP0 HDMI_TX0_P 8 IN_D0P
SN65DP159RGZ HDMI
re-timer U94
AN5 MGTHTXN0 HDMI_TX0_N 9 IN_D0N
AM4 MGTHTXP1 HDMI_TX1_P 5 IN_D1P
AM3 MGTHTXN1 HDMI_TX1_N 6 IN_D1N
AL6 MGTHTXP2 HDMI_TX2_P 2 IN_D2P
AL5 MGTHTXN2 HDMI_TX2_N 3 IN_D2N
AP4 MGTHRXP0 HDMI_RX0_C_P
(1)
B7 TMDS_DATA0_P
P7 MOLEX HDMI
bottom port
AP3 MGTHRXN0 HDMI_RX0_C_N
(1)
B9 TMDS_DATA0_N
AN2 MGTHRXP1 HDMI_RX1_C_P
(1)
B4 TMDS_DATA1_P
AN1 MGTHRXN1 HDMI_RX1_C_N
(1)
B6 TMDS_DATA1_N
AL2 MGTHRXP2 HDMI_RX2_C_P
(1)
B1 TMDS_DATA2_P
AL1 MGTHRXN2 HDMI_RX2_C_N
(1)
B3 TMDS_DATA2_N
AC10 MGTREFCLK1P HDMI_RX_CLK_C_P
(1)
B10 TMDS_CLK_P
AC9 MGTREFCLK1N HDMI_RX_CLK_C_N
(1)
B12 TMDS_CLK_N
AJ6 MGTHTXP3 FMC_HPC1_DP0_C2M_P C2 DP0_C2M_P
FMC HPC1 J4
AJ5 MGTHTXN3 FMC_HPC1_DP0_C2M_N C3 DP0_C2M_N
AK4 MGTHRXP3 FMC_HPC1_DP0_M2C_P C6 DP0_M2C_P
AK3 MGTHRXN3 FMC_HPC1_DP0_M2C_N C7 DP0_M2C_N
AD8 MGTREFCLK0P HDMI_SI5324_OUT_C_P
(1)
28 CKOUT1_P
SI5319C JITTER
ATTEN. U108
AD7 MGTREFCLK0N HDMI_SI5324_OUT_C_N
(1)
29 CKOUT1_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English