Abov MC97F6108A - Page 165

MC97F6108A User’s manual 15. USART
165
UBAUD (USART Baud-Rate Generation Register) FEH
7
6
5
4
3
2
1
0
UBAUD7
UBAUD6
UBAUD5
UBAUD4
UBAUD3
UBAUD2
UBAUD1
UBAUD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
UBAUD [7:0]
The value in this register is used to generate internal baud rate in
asynchronous mode or to generate XCK clock in synchronous or SPI
mode. To prevent malfunction, do not write ‘0’ in asynchronous mode, and
do not write ‘0’ or ‘1’ in synchronous or SPI mode.
UDATA (USART Data Register) FFH
7
6
5
4
3
2
1
0
UDATA7
UDATA6
UDATA 5
UDATA 4
UDATA 3
UDATA 2
UDATA 1
UDATA 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
UDATA [7:0]
The USART Transmit Buffer and Receive Buffer share the same I/O
address with this DATA register. The Transmit Data Buffer is the
destination for data written to the UDATA register. Reading the UDATA
register returns the contents of the Receive Buffer.
Write this register only when the UDRE flag is set. In SPI or synchronous
master mode, write this register even if TX is not enabled to generate
clock, XCK.
Initial value: FFH