Abov MC97F6108A User Manual

15. USART MC97F6108A User’s manual
164
USTAT (USART2 Status Register) FDH
7
6
5
4
3
2
1
0
UDRE
TXC
RXC
WAKE
SOFTRST
DOR
FE
PE
R/W
R/W
R/W
R/W
R/W
R
R
R
Initial value: 80H
UDRE
The UDRE flag indicates if the transmit buffer (UDATA) is ready to be
loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty
and can hold one or two new data. This flag can generate an UDRE
interrupt. Writing ‘0’ to this bit position will clear UDRE flag.
0
Transmit buffer is not empty.
1
Transmit buffer is empty.
TXC
This flag is set when the entire frame in the transmit shift register has been
shifted out and there is no new data currently present in the transmit
buffer. This flag is automatically cleared when the interrupt service routine
of a TXC interrupt is executed. It is also cleared by writing ‘0’ to this bit
position. This flag can generate a TXC interrupt.
0
Transmission is ongoing.
1
Transmit buffer is empty and the data in transmit shift register
are shifted out completely.
RXC
This flag is set when there are unread data in the receive buffer and
cleared when all the data in the receive buffer are read. The RXC flag can
be used to generate a RXC interrupt.
0
There is no data unread in the receive buffer
1
There are more than 1 data in the receive buffer
WAKE
This flag is set when the RX pin is detected low while the CPU is in stop
mode. This flag can be used to generate a WAKE interrupt. This bit is set
only when in asynchronous mode of operation.
NOTE
0
No WAKE interrupt is generated.
1
WAKE interrupt is generated.
SOFTRST
This is an internal reset and only has effect on USART. Writing ‘1’ to this
bit initializes the internal logic of USART and is auto cleared.
0
No operation
1
Reset USART
DOR
This bit is set if a Data OverRun occurs. While this bit is set, the incoming
data frame is ignored. This flag is valid until the receive buffer is read.
0
No Data OverRun
1
Data OverRun detected
FE
This bit is set if the first stop bit of next character in the receive buffer is
detected as ‘0’. This bit is valid until the receive buffer is read.
0
No Frame Error
1
Frame Error detected
PE
This bit is set if the next character in the receive buffer has a Parity Error
when received while Parity Checking is enabled. This bit is valid until the
receive buffer is read.
0
No Parity Error
1
Parity Error detected
NOTE: When the WAKE function of USART is used as a release source from STOP mode,
it is required to clear this bit in the RX interrupt service routine. Else the device will
not wake-up from STOP mode again by the change of RX pin.

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English