Abov MC97F6108A User Manual

MC97F6108A User’s manual 6. Interrupt controller
69
CIENAB (Comparator Interrupt Flag Enable Register) : B1H
7
6
5
4
3
2
1
0
-
-
-
CIENAB4
CIENAB3
CIENAB2
CIENAB1
CIENAB0
-
-
-
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
CIENAB4
Enable or Disable Comparator4 Interrupt
0
Disable Comparator4 interrupt(default)
1
Enable Comparator4 interrupt
CIENAB3
Enable or Disable Comparator3 Interrupt
0
Disable Comparator3 interrupt(default)
1
Enable Comparator3 interrupt
CIENAB2
Enable or Disable Comparator2 Interrupt
0
Disable Comparator2 interrupt(default)
1
Enable Comparator2 interrupt
CIENAB1
Enable or Disable Comparator1 Interrupt
0
Disable Comparator1 interrupt(default)
1
Enable Comparator1 interrupt
CIENAB0
Enable or Disable Comparator0 Interrupt
0
Disable Comparator0 interrupt(default)
1
Enable Comparator0 interrupt
CIFLAG (Comparator Interrupt Flag Register) : ACH
7
6
5
4
3
2
1
0
-
-
-
CMP4IF
CMP3IF
CMP2IF
CMP1IF
CMP0IF
-
-
-
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
When an interrupt source is generated and CIENAB is set to '1', the flag
is generated.
The flag can be cleared by writing a ‘0’ to bit. It is also cleared
automatically before interrupt service routine is served.
CMP4IF
When Comparator4 Interrupt occurs this bit is set.
0
Comparator4 Interrupt not occurred
1
Comparator4 Interrupt occurred
CMP3IF
When Comparator3 Interrupt occurs this bit is set.
0
Comparator3 Interrupt not occurred
1
Comparator3 Interrupt occurred
CMP2IF
When Comparator2 Interrupt occurs this bit is set.
0
Comparator2 Interrupt not occurred
1
Comparator2 Interrupt occurred
CMP1IF
When Comparator1 Interrupt occurs this bit is set.
0
Comparator1 Interrupt not occurred
1
Comparator1 Interrupt occurred
CMP0IF
When Comparator0 Interrupt occurs this bit is set.
0
Comparator0 Interrupt not occurred
1
Comparator0 Interrupt occurred

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English