Figure 99. Flash Memory Map ............................................................................................................ 206
Figure 100. Address Configuration of Flash Memory ......................................................................... 206
Figure 101. The Sequence of Page Program and Erase of Flash Memory ........................................ 207
Figure 102. The Sequence of Bulk Erase of Flash Memory ............................................................... 208
Figure 103. Pin Diagram for Parallel Programming ............................................................................ 214
Figure 104. Parallel Byte Read Timing of Program Memory .............................................................. 216
Figure 105. Parallel Byte Write Timing of Program Memory ............................................................... 216
Figure 106. ISP Mode ......................................................................................................................... 217
Figure 107. Byte-Parallel Mode .......................................................................................................... 217
Figure 108. AC Timing ......................................................................................................................... 225
Figure 109. Waveform for USART Timing Characteristics .................................................................. 227
Figure 110. Timing Waveform for the USART Module ........................................................................ 227
Figure 111. SPI Timing ........................................................................................................................ 228
Figure 112. I2C Timing ........................................................................................................................ 229
Figure 113. STOP Mode Release Timing when Initiated by an Interrupt ............................................ 230
Figure 114. STOP Mode Release Timing when Initiated by RESETB ................................................ 230
Figure 115. Operating Voltage Range ................................................................................................. 232
Figure 116. Recommended Voltage Range ........................................................................................ 232
Figure 117. Output High Voltage (VOH) .............................................................................................. 233
Figure 118. Output Low Voltage (VOL) ............................................................................................... 234
Figure 119. 20 SOP Package Outline ................................................................................................. 235
Figure 120. 16 SOPN Package Outline .............................................................................................. 236
Figure 121. MC97F6108A Device Numbering Nomenclature ............................................................. 237
Figure 122. Debugger (OCD1/OCD2) and Pinouts ............................................................................ 239
Figure 123. E-PGM+ (Single Writer) and Pinouts ............................................................................... 239
Figure 124. E-Gang4 and E-Gang6 (for Mass Production) ................................................................ 240
Figure 125. PCB Design Guide for On-Board Programming .............................................................. 242
Figure 126. On-Chip Debugging System in Block Diagram ................................................................ 244
Figure 127. 10-bit Transmission Packet .............................................................................................. 245
Figure 128. Data Transfer on Twin Bus .............................................................................................. 246
Figure 129. Bit Transfer on Serial Bus ................................................................................................ 246
Figure 130. Start and Stop Condition .................................................................................................. 246
Figure 131. Acknowledge on Serial Bus ............................................................................................. 247
Figure 132. Clock Synchronization during Wait Procedure ................................................................ 247
Figure 133. Connection of Transmission ............................................................................................ 248