Abov MC97F6108A User Manual

List of figures MC97F6108A User’s manual
8
Figure 49. Auto Period Mode Block Diagram (ATPSEL = 2'b1x) ........................................................ 107
Figure 50. Auto Period Mode (ATPSEL = 2'b1x) ................................................................................ 108
Figure 51. PPG Period Block Diagram When Writing ......................................................................... 109
Figure 52. PPG Period When Writing (ATPSEL = 2'b1x) ................................................................... 110
Figure 53. Max and Min Period Limitation .......................................................................................... 111
Figure 54. PPG Period Block Diagram When Period Min/Max Matching ........................................... 112
Figure 55. When Max Period Matching ............................................................................................... 112
Figure 56. When Min Period Matching ................................................................................................ 113
Figure 57. PPG Off-time Max/Min Limitation Block Diagram .............................................................. 114
Figure 58. PPG Off-time Max/Min Limitation ...................................................................................... 115
Figure 59. Analog Comparator and OP-AMP Block Diagram ............................................................. 128
Figure 60. Buzzer Driver Block Diagram ............................................................................................. 138
Figure 61. 12-bit ADC Block Diagram ................................................................................................. 141
Figure 62. A/D Analog Input Pin with a Capacitor ............................................................................... 141
Figure 63. A/D Power (AVREF) Pin with a Capacitor.......................................................................... 141
Figure 64. Control Registers and Align Bits ........................................................................................ 142
Figure 65. ADC Operation Flow Sequence ......................................................................................... 143
Figure 66. USART Block Diagram ...................................................................................................... 148
Figure 67. Clock Generation Block Diagram ....................................................................................... 149
Figure 68. Synchronous Mode XCK Timing ........................................................................................ 150
Figure 69. A Frame Format ................................................................................................................. 151
Figure 70. Start Bit Sampling .............................................................................................................. 155
Figure 71. Sampling of Data and Parity Bit ......................................................................................... 156
Figure 72. Stop Bit Sampling and Next Start Bit Sampling ................................................................. 156
Figure 73. SPI Clock Formats when UCPHA = 0 ................................................................................ 158
Figure 74. SPI Clock Formats when UCPHA = 1 ................................................................................ 159
Figure 75. I2C Block Diagram ............................................................................................................. 168
Figure 76. Bit Transfer on the I2C-Bus ............................................................................................... 169
Figure 77. START and STOP Condition.............................................................................................. 169
Figure 78. Data Transfer on the I2C-Bus ............................................................................................ 170
Figure 79. Acknowledge on the I2C-Bus ............................................................................................. 171
Figure 80. Clock Synchronization during Arbitration Procedure ......................................................... 172
Figure 81. Arbitration Procedure of Two Masters ................................................................................ 172
Figure 82. IDLE Mode Release Timing by an External Interrupt ........................................................ 185
Figure 83. IDLE Mode Release Timing by an RESETB ...................................................................... 185
Figure 84. STOP Mode Release Timing by External Interrupt ............................................................ 186
Figure 85. STOP Mode Release Timing by RESETB ......................................................................... 187
Figure 86. STOP1, 2 Mode Release Flow .......................................................................................... 188
Figure 87. Reset Block Diagram ......................................................................................................... 190
Figure 88. Reset Noise Canceller Time Diagram................................................................................ 191
Figure 89. Fast VDD Rising Time ....................................................................................................... 191
Figure 90. Internal RESET Release Timing On Power-Up ................................................................. 192
Figure 91. Configuration Timing when Power-on ................................................................................ 192
Figure 92. Boot Process Waveform .................................................................................................... 193
Figure 93. Timing Diagram after RESET ............................................................................................ 194
Figure 94. Oscillator Generating Waveform Example ......................................................................... 194
Figure 95. BOD Block Diagram ........................................................................................................... 195
Figure 96. Internal Reset at Power Fail Situation ............................................................................... 195
Figure 97. Configuration Timing When LVR RESET........................................................................... 196
Figure 98. Read Device Internal Checksum (Full Size: 0x0000~0x1FFF) ......................................... 204

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English