System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-8
ID073015 Non-Confidential
MPU control and
configuration
Data Fault Status c5, Data Fault Status Register on page 4-48
Auxiliary Fault Status c5, Auxiliary Fault Status Registers on page 4-49
Instruction Fault Status c5, Instruction Fault Status Register on page 4-49
Instruction Fault Address c6, Instruction Fault Address Register on page 4-51
Data Fault Address c6, Data Fault Address Register on page 4-51
MPU Type c0, MPU Type Register on page 4-17
Region Base Address c6, MPU Region Base Address Registers on page 4-52
Region Size and Enable c6, MPU Region Size and Enable Registers on page 4-53
Region Access Control c6, MPU Region Access Control Registers on page 4-54
Memory Region Number c6, MPU Memory Region Number Register on page 4-57
Correctable Fault Location register Correctable Fault Location Register on page 4-75
Cache control and
configuration
Cache Type c0, Cache Type Register on page 4-15
Current Cache Size Identification c0, Current Cache Size Identification Register on page 4-34
Current Cache Level c0, Current Cache Level ID Register on page 4-35
Cache Size Selection c0, Cache Size Selection Register on page 4-36
c7, Cache Operations Cache operations on page 4-58
c15, Invalidate all data cache
Interface control and
configuration
TCM Status c0, TCM Type Register on page 4-16
Region • c9, BTCM Region Register on page 4-61
• c9, TCM Selection Register on page 4-63
Slave Port Control c11, Slave Port Control Register on page 4-63
System performance
monitoring
Performance monitoring Chapter 6 Events and Performance Monitor
Validation System validation Validation Registers on page 4-66
a. Known as the ID Code Register on previous designs. Returns the device ID code.
Table 4-1 System control coprocessor register functions (continued)
Function Register/operation Reference to description
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