251
7647H–AVR–03/12
Atmel ATmega16/32/64/M1/C1
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion
is started. In case the amplifier output is modified during the sample phase of the ADC, the
on-going conversion is aborted and restarted as soon as the output of the amplifier is stable.
This ensure a fast response time. The only precaution to take is to be sure that the trig signal
(PSC) frequency is lower than ADCclk/4.
Figure 18-15. Amplifier synchronization timing diagram
With change on analog input signal
Valid sample
Delta V
4th stable sample
Signal to be
measured
AMPLI_clk
(Sync Clock)
CK ADC
PSCn_ASY
PSC
Block
ADSC
ADC
Activity
ADC
ADC
Sampling
ADC
Co n v
ADC
Sampling
ADC
Co n v
ADC Result
Ready
ADC Result
Ready
To Next Page
Loading...
Need help?
General
