12 CPU System
12-2 FLO-GARD 6301 DUAL CHANNEL VOLUMETRIC INFUSION PUMP SERVICE MANUAL 07-19-B1-729
Q Monitors motor skip steps by checking the signals from the motor
rotation detectors.
Q Controls the motor currents while minimizing current draw from the
battery. It also controls the alarm control circuit.
The slave CPU outputs an interrupt signal to the master CPU through the
universal pulse processor after every one-eighth of the liveband period to
provide air bubble detection timing to the master CPU.
Both CPUs handle the watchdog function, which is the periodic
communication between the CPUs through two serial communication lines at
15,625 baud.
The CPUs utilize 16 address and eight data lines and can access 64Kb. The
master CPU addresses 128K x 8 EPROMs through two bank address lines.
The master CPU addresses an EPROM, RAM, Real Time Clock, universal
pulse processor, two I/O controllers and the communication controller. The
slave CPU addresses an EPROM, RAM and programmable timer module.
The software in the EPROMs for master and slave CPUs is different.
Programmable Timer Module (PTM)
See Figure 13-12. The programmable timer module (PTM) divides the 8 MHz
system clock into 500 kHz for the oscillation of the air sensors and also
generates a signal for pulse width modulation control of the motor drivers.
The slave CPU calculates and outputs motor drive signals based on the rate
information from the master CPU. It also sets motor current levels in the PTM
from a reference table.
Watchdog Function
The watchdog function is performed in two ways.
Both CPUs monitor each other’s status. The purpose of this watchdog is to
detect a malfunction of either microprocessor and stop the pumps with an
alarm. See Figure 13-10 and Figure 13-16. Both CPUs communicate through
the two serial communication lines, Tx and Rx. Each CPU has a
communication counter, which is initialized to a predetermined value by a
signal from the other CPU. The counter is then decremented by one count
every 32.768 mS. The counters are normally initialized again by the signal
from the other CPU before they decrement to zero. When a counter reaches
zero, it indicates that the watchdog signal from the other CPU was never
received. This indicates a problem with the other CPU. The remaining
functional CPU then stops the pumps with visual and audible alarms.
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