5320A
Users Manual
5-46
Table 5-9. Bit Configuration of the Event Status Register
Bit Name Event Description
PON Power On (bit 7). This bit is set to “1” when an off-to-on transition has occurred in
the Calibrator’s power supply.
URQ User Request (bit 6). This bit is not used by the Calibrator. It is always a “0”.
CME Command Error (bit 5). This bit is set to “1” whenever a incorrectly formatted
command or query has been detected by the Calibrator.
EXE Execution Error (bit 4). This bit is set to “1” whenever a received command can
NOT be executed, owing to the device state or the command parameter is out of
limits.
DDE Device Dependent Error (bit 3). This bit is set to “1” whenever the Calibrator
detects an error that is not a command error, a query error, nor an execution error.
A device-specific error is any excuted Calibrator operation that did not properly
complete due to some condition, such as an overload.
QYE Query Error (bit 2). This bit is set to “1” whenever the Calibrator is addressed as a
talker and the output queue is empty, or if the control unit did not pick up a
response before sending the next query.
OPC Operation Complete (bit 0). This bit is set in response to the *OPC command. It
indicates the Calibrator has completed all selected pending operations.
ESE Event Status Enable Register
The Event Status Enable Register allows one or more events in the Event Status
Register to be reflected in the ESB summary-message bit. This register has 8 bits,
each corresponding to the bits in the Event Status Register. The Event Status Enable
Register is read with the common query *ESE?. Data is returned as a binary-
weighted value. The Event Status Enable Register is written to by the common
command, *ESE. Sending the *ESE common command followed by a zero clears the
ESE. The Event Status Enable Register is cleared upon power-on.
The ESE register suppresses or allows bits in ESR register. A value of “0“ in a bit of
the ESE register suppresses (masks) the influence of the appropriate bit in the ESR
register. Setting of any unmask bit of the ESR register results in setting of the ESB
status register. The ESE register value can be modified by the *ESE command
followed by the value of the mask register (integer in range 0 –255). Reading of the
register can be performed with the *ESE? command. The register is automatically
reset after powering up the Calibrator. The register is not reset with *CLS command.
Operation Status Register
The following “sticky” bits in the Operation register are set by their associated
conditions. Bit 8 is set when RCD trip current has been reached and time counting is
in progress. The setting to the Transition Filter is fixed (1 → 0 change). Bit 8 in the
Event Register is set after the RCD Trip Time has expired.
Questionable Status Register
Not used in the Calibrator.
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