Remote Operation
Supported SCPI Commands 5
5-45
Table 5-8. Bit Configuration of the Status Byte Register
Bit Name Description
OSS Operation Summary Status (bit 7). SCPI-defined. The OSS bit is set to 1 when
the data in the OSR (Operation Status Register) contains one or more enabled
bits which are true.
RQS Request Service (bit 6). The bit is read as a part of status byte only when serial
message is sent.
MSS Master Summary Status (bit 6). The MSS bit is set to 1 whenever bits ESB or
MAV are 1 and enabled (1) in the SRE. This bit can be read using the *STB?
Command. This value is derived from STB and SRE status.
ESB Event Summary Bit (bit 5). This value is derived from STB and SRE status. The
ESB bit is set to 1 when one or more enabled ESR bits are set to 1.
MAV Message Available (bit 4). The MAV bit is set to 1 whenever data is available in
the IEEE 488 Output Queue (the response on query is “ready”).
QSS Questionable Summary Status (bit 3). SCPI-defined. The QSS bit is set to 1
when the data in the QSR (Questionable Status Register) contains one or more
enabled bits which are true.
SRE Service Request Enable Register
The SRE Register is an 8-bit register that enables or disables (masks) corresponding
summary messages in the Status Byte Register.
The meter may be programmed to make a service request on errors, questionable
data, or when output is available. Conditions that trigger a service request are
specified by writing a binary weighted value to the SRE Register, using the *SRE
command.
If any bit in the SRE is set to 1, the RQS bit (bit 6) in the Status Byte Register is
enabled, meaning a service request can be generated when the appropriate bits in
STB become 1. At power-up, or on any device-clear command, the SRE Register is
set to 00 (decimal). The register is not reset by the *CLS command.
ESR Event Status Register
Every bit of the Event Status Register corresponds to one event. Bit is set when the
event is changed and it remains set also when the event passed. The ESR is cleared
when the power is turned on (except bit PON which is set), and every time it is read
via command *ESR? or cleared with *CLS.
To Next Page
Loading...
