Intel Core 2 Duo Processor User Manual

Development Board Features
30 Development Kit User’s Manual
3.5 Thermal Management
The objective of thermal management is to ensure that the temperature of each
component is maintained within specified functional limits. The functional temperature
limit is the range within which the electrical circuits can be expected to meet their
specified performance requirements. Operation outside the functional limit can
degrade system performance and cause reliability problems.
The development kit is shipped with a heatsink thermal solution for installation on the
processor. This thermal solution has been tested in an open-air environment at room
temperature and is sufficient for development purposes. The designer must ensure
that adequate thermal management is provided for if the system is used in other
environments or enclosures.
3.6 System Features and Operation
The following sections provide a detailed view of the system features and operation of
the development board.
3.6.1 Processor Support
The Silver Cascade board design supports the Intel® Core™ 2 Duo processor T9400
(U2E1) in a 478-pin Micro-FCPGA (Flip Chip Pin Grid Array) package.
3.6.2 Processor Voltage Regulators
The reference board implements an onboard Intel® Mobile Voltage Positioning
Intel® MVP -6 regulator for the processor core supply. The core VR solution supports
PSI2. The VR will support up to 56 amps. Slow C4 exit is supported to reduce
perceptible audio noise caused by periodically exiting the C4 state.
3.6.3 Front-Side Bus (FSB)
The Front Side Bus (FSB) on the development board supports data rates of 667 MT/s
(167MHz quad pumped, FSB-667), 800 MT/s (200MHz quad pumped, FSB-800) &
1067 MT/s (266 MHz quad pumped, FSB-1067). The FSB is AGTL+ and will be running
at 1.05V.
3.6.4 Processor Power Management
Intel® Core™ 2 Duo processor T9400 supports C0-C6 power states. This processor
also supports C2E and C4E. Additionally, the processor supports a new processor
state, Intel Deep Power Down Technology, that brings the CPU leakage power down to
the lowest possible. DPWR# protocol is also supported on the development board
through signal H_DPWR#.

Intel Core 2 Duo Processor Specifications

General

Number of Cores	2
Manufacturing Process	65nm or 45nm (depending on model)
Execute Disable Bit	Yes
Enhanced Intel SpeedStep Technology	Yes
L2 Cache	2MB, 4MB, or 6MB (depending on model)
Front Side Bus	1066 MHz
Thermal Design Power (TDP)	35W - 65W (depending on model)
Socket Type	LGA775
Clock Speed	1.6 GHz - 3.33 GHz (depending on model)
Instruction Set	x86, x86-64
Virtualization Technology	Yes (depending on model)
Architecture	Intel Core Microarchitecture