Development Board Features
32 Development Kit User’s Manual
3.6.9 Video Display
The reference board has six options for displaying video: VGA, LVDS, TVOUT, SDVO,
Display port (through Add in card) or PCI Express Graphics (PEG). Display port, SDVO
and PCI Express Graphics (PEG) are multiplexed on the same pins within the chipset.
The development board contains one DP/SDVO/PCI Express Graphics Slot (J6B2) for a
PCI Express compatible graphics card or an SDVO compatible graphics card (ADD2N &
ADD2R), one LVDS connector (J6F1), one TV-OUT D-connector (J2A1), and one 15-pin
VGA connector (J2A2). To support ADD2R (with PCI graphic lanes reversed), resistor
R1U4 should be made “NO STUFF”.
By default the voltage supplied to the SDVO/PCI Express Graphics slot is switched off
in suspend mode, and the reset signal is not gated. A stuffing option allows the
voltage to be supplied from voltage rails that stay on in suspend mode. A different
stuffing option allows the reset signal to be gated as well. Details of these stuffing
options can be referred on page 19 of the Silver Cascade schematics.
The TV is output through a D-connector. There are two cables in order to access TV: a
black D-connector to S-video (IPN: C87694-001) and a black D-connector to 3 pin
component (IPN: C87695-001). The blue coax pin can be used for composite TV
interface. To use a non-high definition external display with the board, change the
resolution to 480 lines interlaced (480i) in the Internal Graphics Device properties.
Table 7. TV–Out Connections
D-connector Cable
Composite Video
Blue
Cable TV
Red Red
Green Green
Component Video
Blue Blue
S–Video
D-connector to S-video
Note: Composite video and component video both use the same cable.
3.6.10 PCIe Slots
The ICH9M I/O Controller Hub (ICH9M) provides 6 PCIE ports (x1). Port 6 is
multiplexed with Gigabit LAN Controller Interface. The reference board has five x1
PCIe slots (J6B1, J6D1, J8B3, J8D1 & J7B1). Three of the five slots, Slot 1, Slot 3, and
Slot 5, are located at standard expansion slot locations. The fourth and fifth slots, Slot
2 and Slot 4, are located in-line with Slot 1 and Slot 3 respectively.
Support for x2 on lane 1 and lane 2 (Port 1 can be configured as a x1 port or a x2 port
shared with port 2) and on Lane 3 and lane 4 (port 3 can be configured as a x1 port or
a x2 port shared with port 4) can be configured via the ICH9M “RPC – Root Port
Configuration” register.
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