Keysight 81150A - Pulse Waveform Generation

Tutorial
81150A and 81160A User’s Guide 607
7.3 Pulse Waveform Generation
Introduction
The Keysight 81150A / 81160A uses a modified DDS scheme for pulse,
square and ramp waveform generation.
The full 64 bit phase information is used for the timing calculations. Every
sample for the waveform DAC is computed by arithmetic-logic units. This
prevents the need to reprogram a waveform memory if one of the pulse
parameter changes.
All timing changes are synchronized with the pulse period so that there are
no glitches in the output signal as long as the period is small. Signal
generation will be reset if the period is greater than 100 ms to guarantee
reasonable response times when changing the timing parameters.
The pulse waveform generation logic is represented in the diagram shown
below for the 81150A.
The 81160A uses a 2.5 GHz clock.
Rising Edge
Computation
Falling Edge
Computation
High Level
Sample
Low Level
Sample
Waveform
DAC
Anti-Aliasing
Filter
2 GHz
DDS
Phase
Information
Pulse Section
Evaluation
Rise Time
Fall Time
Width
64 Bits
Pulse Generation Block Diagram