Keysight 81150A - External in to Trigger out Timing

Tutorial
81150A and 81160A User’s Guide 627
7.7 External In to Trigger Out Timing
Introduction
The Keysight 81150A / 81160A has a constant timing between the signal
provided at the External-In connector and the response at the Trigger Out
connector. This latency is independent to the output frequency being
generated, but depends on the overall mode of operation (the latency is
bigger for triggered or gated frequency sweeps). To achieve this constant
latency, the logic depicted in the following block diagram is used.
The 81160A uses a 2.5 GHz ADC.
ADC
Data
Transition
Time
Converter
+
-
Logic DDS
Start
Phase
Correction
1 GHz
External In
Threshold
Voltage
External-In Block Diagram of 81150A
The signal applied to External-In is first compared against the threshold
voltage. The digitized External-In signal is then fed through a transition time
converter. This guarantees that the signal that is sampled by the ADC has a
well known transition time, which is greater than the sampling interval. The
required phase offset for the DDS is calculated from the first 2 ADC readings
that are not clipped to the ADC’s minimum reading as shown below.