Mitsubishi Electric MELSEC iQ-F Series - Cyclic data assurance

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4 FUNCTIONS
4.2 Cyclic Transmission
Cyclic data assurance
This function assures the cyclic data integrity in units of 32 bits or station-based units.
: Assured, : Not assured
When a remote station is in the network, use station-based block data assurance. If it is disabled, the
functions of the remote station cannot be assured.
32-bit data assurance
Assures RWr and RWw data in 32-bit units.
Data assurance at the time of access to link devices
When link refresh target devices are accessed, the integrity of 32-bit data can be assured by satisfying the following
conditions:
• The start device number of RWr and RWw is a multiple of 2
• The number of points assigned to RWr and RWw is a multiple of 2.
Data assurance at the time of access to buffer memory
The integrity of 32-bit data can be assured by satisfying the following conditions:
• Access using the DMOV instruction
• The start address of the buffer memory is a multiple of 2.
Method Description Link refresh Access to buffer
memory
32-bit data assurance Assures data in 32-bit units.
Data is automatically assured by satisfying assignment conditions of link
devices.

Station-based block data
assurance
Assures data in station-based units.
Data is assured by enabling the station-based block data assurance in
the parameter setting.

Interlock program Assures data of more than 32 bits.
Data is assured by configuring interlocks on programs.

0H
1H
2H
3H
4H
5H
6H
7H
FX5-CCLGN-MS
RWr, RWw
2 words
(32 bits)
FX5 CPU module
Device
Link refresh
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
0H
1H
2H
3H
4H
5H
6H
7H
DMOV K100 G10240
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
DMOV instruction
FX5-CCLGN-MS
Buffer memory
U1\