Mitsubishi Electric MELSEC-Q/L - Page 1022

1020
APPENDICES
Appendix 1 Operation Processing Time
Data link
instruction
S.ZCOM When mounting CC-Link module (master
station side)
7.100 25.000 7.100 25.000 7.100 25.000
When mounting CC-Link module (local
station side)
7.100 25.200 7.100 25.200 7.100 25.200
• When selecting MELSECNET/H refresh
only (control station side)
• When selecting CC-Link IE Controller
Network refresh only (control station side)
18.400 48.300 18.400 48.300 18.400 48.300
• When selecting MELSECNET/H refresh
only (normal station side)
• When selecting CC-Link IE Controller
Network refresh only (normal station side)
18.400 43.500 18.400 43.500 18.400 43.500
When selecting CC-Link IE Field Network
refresh only (master station side)
12.000 38.500 12.000 38.500 12.000 38.500
When selecting CC-Link IE Field Network
refresh only (local station side)
11.900 41.900 11.900 41.900 11.900 41.900
S.RTREAD  2.900 15.400 2.900 15.400 2.900 15.400
S.RTWRITE  3.100 15.600 3.100 15.600 3.100 15.600
S.REFDVWRB When the refresh device as the write target
exists at Transfer 1
34.500 51.000 34.500 51.000 34.500 51.000
When the refresh device as the write target
exists at Transfer 256
91.000 109.000 91.000 109.000 91.000 109.000
S.REFDVWRW When the refresh device as the write target
exists at Transfer 1
34.500 51.000 34.500 51.000 34.500 51.000
When the refresh device as the write target
exists at Transfer 256
91.000 109.000 91.000 109.000 91.000 109.000
S.REFDVRDB When the refresh device as the read target
exists at Transfer 1
34.500 51.000 34.500 51.000 34.500 51.000
When the refresh device as the read target
exists at Transfer 256
91.000 109.000 91.000 109.000 91.000 109.000
S.REFDVRDW When the refresh device as the read target
exists at Transfer 1
34.500 51.000 34.500 51.000 34.500 51.000
When the refresh device as the read target
exists at Transfer 256
91.000 109.000 91.000 109.000 91.000 109.000
Multiple
CPU
dedicated
instruction
S.TO n1 n2 n3 n4 (D) Writing to host CPU
shared memory
n4=1 14.700 30.000 14.700 30.000 14.700 30.000
n4=320 48.700 62.900 48.700 62.900 48.700 62.900
TO n1 n2 (S) n3 Writing to host CPU
shared memory
n3=1 3.700 18.200 3.700 18.200 3.700 18.200
n3=320 36.500 50.800 36.500 50.800 36.500 50.800
DTO n1 n2 (S) n3 Writing to host CPU
shared memory
n3=1 3.700 18.600 3.700 18.600 3.700 18.600
n3=320 68.700 82.700 68.700 82.700 68.700 82.700
FROM n1 n2 (D) n3 Reading from host
CPU shared memory
n3=1 3.700 17.500 3.700 17.500 3.700 17.500
n3=320 27.400 41.000 27.400 41.000 27.400 41.000
Reading from other
CPU shared memory
n3=1 5.100 28.000 5.100 28.000 5.100 28.000
n3=320 125.600 152.100 125.600 152.100 125.600 152.100
n3=1000 386.000 413.900 386.000 413.900 386.000 413.900
DFRO n1 n2 (D) n3 Reading from host
CPU shared memory
n3=1 3.700 17.500 3.700 17.500 3.700 17.500
n3=320 51.500 65.000 51.500 65.000 51.500 65.000
Reading from other
CPU shared memory
n3=1 5.700 30.300 5.700 30.300 5.700 30.300
n3=320 246.700 272.000 246.700 272.000 246.700 272.000
n3=1000 764.500 792.800 764.500 792.800 764.500 792.800
Category Instruction Condition (device) Processing time (s)
Q03UDVCPU Q04UDVCPU Q06UDVCPU,
Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.