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Mitsubishi Electric MELSEC-Q/L - Page 455

Mitsubishi Electric MELSEC-Q/L
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7 APPLICATION INSTRUCTIONS
7.5 Data Processing Instructions
453
7
Calculation of horizontal parity value
In 16-bit conversion mode, the shaded part in the following figure becomes the calculation target of the horizontal parity. The
number of ON (1) bits is calculated to determine the parity value which becomes ON (1) when the number of ON (1) bits is
finally odd or OFF (0) when it is finally even, and the horizontal parity value is stored in the device specified by (S)+1.
8-bit conversion mode (when SM772 is ON)
For the n points of data (lower 8 bits only) starting from (S), the added data and horizontal parity data are stored in the
devices (D) and (D)+1 respectively. An example when n = 6 is shown below.
Calculation of addition data value
In 8-bit conversion mode, added data is obtained by adding 6 bytes at the shaded positions in the following figure. Here,
added data is "03B2H" and accordingly "03B2H" is stored in the device specified by (D).
Calculation of horizontal parity value
In 8-bit conversion mode, the shaded part in the following figure becomes the calculation target of the horizontal parity. The
number of ON (1) bits is calculated to determine the parity value which becomes ON (1) when the number of ON (1) bits is
finally odd or OFF (0) when it is finally even, and the horizontal parity value is stored in the device specified by (S)+1.
01100001 61
H
Upper 8 bits of D0
b7 b6 b5 b4 b3 b2 b1 b0Device
01100100 64
H
Lower 8 bits of D0
00010000 10
H
Upper 8 bits of D1
01111011 7B
H
Lower 8 bits of D1
11111010 7A
H
Upper 8 bits of D2
11001011 CB
H
Lower 8 bits of D2
01011111 5F
H
Horizontal parity
This value is stored in +1.
D
Device Decimal
Hexadecimal
Upper bits Lower bits
61
H 64H
10H 7BH
FAH CBH
FFH FFH
7FH F9H
27H 10H
D0 24932
D1 4219
D2 -1333
D3 -1
D4 32761
D5 10000
b7 b6 b5 b4 b3 b2 b1 b0Device
Horizontal parity
This value is stored in +1.
D
01100100 64
H
Lower 8 bits of D0
01111011 7B
H
Lower 8 bits of D1
11001011 CB
H
Lower 8 bits of D2
11111111 FF
H
Lower 8 bits of D3
11111001 F9
H
Lower 8 bits of D4
00010000 10
H
Lower 8 bits of D5
11000010 C2
H

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