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10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
10.1 Overview
Managing the multiple CPU high speed transmission area
The multiple CPU high speed transmission area is managed by blocks in units of 16 words.
The following table shows the number of blocks that can be used in each CPU and the number of blocks used in the
instruction.
*1 For setting of the system area, refer to the QCPU User's Manual (Multiple CPU System).
The following shows configuration of the multiple CPU high speed transmission area when the multiple CPU system is
configured with three CPU modules and the system area size is 1K word.
Number of blocks used for the instruction
The number of blocks used for the instruction depends on the number of write points.
The following table shows the number of blocks used for the instruction.
Number of CPU modules System area
*1
1K points 2K points
246110
32254
41435
Number of write/read points specified by
the instruction
D(P).DDWR instruction D(P).DDRD instruction
1 to 4 1 1
5 to 20 2
21 to 36 3
37 to 52 4
53 to 68 5
69 to 84 6
85 to 100 7
Multiple CPU high speed
transmission area in
CPU No.1
Multiple CPU high speed
transmission area in
CPU No.2
Multiple CPU high speed
transmission area in
CPU No.3
22
blocks
22
blocks
22
blocks
22
blocks
Send area
(to CPU No.2)
Send area
(to CPU No.3)
Receive area
(from CPU
No.1)
Receive area
(from CPU
No.1)
22
blocks
Receive area
(from CPU
No.2)
Send area
(to CPU No.1)
Send area
(to CPU No.3)
22
blocks
22
blocks
Receive area
(from CPU
No.2)
22
blocks
22
blocks
Receive area
(from CPU
No.3)
22
blocks
Receive area
(from CPU
No.3)
Send area
(to CPU No.1)
Send area
(to CPU No.2)
22
blocks
22
blocks
Data send area from CPU No.1 to CPU No.2 and No.3
Data send area from CPU No.2 to CPU No.1 and No.3
Data send area from CPU No.3 to CPU No.1 and No.2
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