10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
10.2 Writing Devices to Another CPU
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• In multiple CPU system, data stored in a device specified by host CPU (S2) or later is stored by the number of write points
specified by ((D2)+1) into a device specified by another CPU (n) (D1) or later.
• Whether to complete the D(P).DDWR instruction normally can be checked by the completion device ((D2)+0) and
completion status display device ((D2)+1).
• The number of blocks used for the instruction depends on the number of write points (Page 861 Overview)
Number of blocks used for the instruction
• The instruction will be completed abnormally when there are no empty blocks in the multiple CPU high speed transmission
area. Set the number of blocks used for the instruction at special registers (SD796 to SD799), and use the special relays
(SM796 to SM799) as an interlock prevent error completion (Page 861 Overview)
• Completion device ((D2)+0)
Turns on at END processing in the scan where the instruction has been completed, and turns off at the next END processing.
• Completion status display device ((D2)+1)
This device turns on/off depending on the status upon completion of the instruction.
Normal completion: Off
Error completion: Turns on at END processing in the scan where the instruction has been completed, and turns off at the next END processing. (At error
completion, an error code is stored at control data ((S1)+0): Completion status.)
Number of write points specified by the instruction D(P).DDWR instruction
1 to 4 1
5 to 20 2
21 to 36 3
37 to 52 4
53 to 68 5
69 to 84 6
85 to 100 7
Start device number of the
storage location for read data
D2
Number of read points
S1 +1
Host CPU
(CPU that requests reading)
Another CPU n
(CPU to be read)
Start device number of the storage
location where read has been stored
S1
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