10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
10.2 Writing Devices to Another CPU
875
10
• Digit specification of bit device is possible for n, (S2), and (D1). Note that when the digit specification of bit device is made
to (S2) or (D1), the following conditions must be met.
• Execute this instruction after checking that the write target CPU is powered on. Not doing so may end up no processing.
• If changing a range of the device specified at setting data between after execution of the instruction and turn-on of the
completion device, data to be stored by system (completion status, completion device) cannot be stored normally.
• SB, SW, SM, and SD include system information area. Take care not to destroy the system information when writing data to
the SB, SW, SM, and SD with the D(P).DDWR instruction of the multiple CPU high-speed transmission dedicated
instruction.
• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10H).
To Next Page
Loading...
