Mitsubishi Electric MELSEC-Q/L - Page 947

APPENDICES
Appendix 1 Operation Processing Time
945
A
• When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU
Device name Data Device specification
location
Addition time (s)
Q03UDVCPU Q04UDVCPU Q06UDVCPU,
Q13UDVCPU,
Q26UDVCPU
File register (R) When the
extended SRAM
cassette is not
used
Bit Source 0.074 0.043 0.043
Destination 0.023 0.023 0.023
Word Source 0.074 0.043 0.043
Destination 0.023 0.023 0.023
Double word Source 0.148 0.085 0.085
Destination 0.044 0.044 0.044
When the
extended SRAM
cassette is used
Bit Source 0.099 0.099 0.099
Destination 0.028 0.028 0.028
Word Source 0.099 0.099 0.099
Destination 0.028 0.028 0.028
Double word Source 0.198 0.198 0.198
Destination 0.054 0.054 0.054
File register (ZR),
extended data
register (D),
extended link
register (W)
When the
extended SRAM
cassette is not
used
Bit Source 0.074 0.043 0.043
Destination 0.023 0.023 0.023
Word Source 0.074 0.043 0.043
Destination 0.023 0.023 0.023
Double word Source 0.148 0.085 0.085
Destination 0.044 0.044 0.044
When the
extended SRAM
cassette is used
Bit Source 0.099 0.099 0.099
Destination 0.028 0.028 0.028
Word Source 0.099 0.099 0.099
Destination 0.028 0.028 0.028
Double word Source 0.198 0.198 0.198
Destination 0.054 0.054 0.054
Module access device (Multiple CPU
high speed transmission area)
(U3En\G10000)
Bit Source 0.042 0.042 0.042
Destination 0.049 0.049 0.049
Word Source 0.042 0.042 0.042
Destination 0.049 0.049 0.049
Double word Source 0.092 0.092 0.092
Destination 0.095 0.095 0.095