6300
J201
provides a path
for
the
majority
of
logic
command signals
for
the
positioner
servo
system from
the
Logic
PCBA
to
the Servo PCBA. J202 provides a path
for
the remaining
logic signals from
the
Logic PCBA
to
the Servo PCBA, and vice versa.
5.3.2.1 Velocity
Function
Generator
The Velocity Function Generator
is
shown on Schematic No. 102810, sheet 1. This
circuit
generates a step voltage signal
of
known polarity (positive
or
negative) which can be
monitored
at
TP9 (zone H1S). The polarity
of
this
signal is dependent upon the state
of
logic command signals NLADOG, NLAD1G, NLAD2G, NLAD3G, NLAD4G, NLADSG,
NLAD6G, NLAD7G, NLADEG, and LFDX1. Assume that the address difference is non-zero
and is such that the signals
at
pin 19, 18, 27, 28, 29, 30, 33, 31,
32
of
J201
are in the logic
low
state, i.e., signals are active. Correspondingly, the
output
logic
state
of
ICs U3-A,
U3-B, U3-C, U3-D, and
US-A,
US-D
will
be
high
causing diodes CR1, CR3,
CRS,
CR7, CR9,
and
CR11
to
be reverse-biased.
Diodes CR2, CR4, CR6, CR8,
CR10, and CR12 are forward-biased and current
flowing
through resistor network
R1
and
R2,
R7
and
R8,
etc.,
is
summed at
the
summing
junction
(pin
2)
of
operational
amplifier
U8
(zone H1S). The
otput
at
TP9
will
be
+6v
depending on
the state
of
Forward Direction (LFDX1)
logic
signal. When
LFDX1
is high, the
output
at
TP9
will
be
+6v
and when
LFDX1
is
low,
the
output
at
TP9
will
be
-6v.
Similarly, when
the address difference
is
zero, the state
of
the
logic
command signals NLADOG through
NLADEG is such that the
output
logic
state
of
ICs U3-A, U3-B, U3-C, U3-D, and US-A,
US-D
will
be
low,
and diodes CR1, CR3,
CRS,
CR7, CR9,
CR11
will
be forward-biased.
Diodes CR2, CR4, CR6, CR8, CR10, and CR12 are reverse-biased and no current
flows
from the resistor network
into
the
summing
junction
of
U8
excepl from
R24
and
R2S.
Consequently, the
output
at TP9
will
be
+0.3v
depending on the state
of
logiC signal
LFDX1.
A third
possibility
exists when the address difference
is
non-zero and the state
of
signals
NLADOG
through NLADEG
is
such that some
of
the
output
logiC states at the
outputs
of
U3-A, U3-B, U3-C, U3-D, and US-A,
U-SD
are high and others are low. In that case, the
output
at TP9
will
be a voltage step in between + 6v and + 0.3v depending on the
output
logiC states
of
U3-A, U3-B, U3-C, U3-D, and US-A, US-D.
Veloci~y
Reference Enable (NLVREG) going
low
at
pin
20
of
J201
turns
03
(zone
F1S)
on
and current
flows
from TP9 through
R1S
and
into
the
summing
junction
(pin
2)
of
the
summing
amplifier
U16 (zone G12). When NLVREG
is
high,
03
is turned
off
and no current
flows
into
the
summing
junction
of
U16. Hence, FET
03
acts as a
switch
which enables
the velocity reference signal
at
TP9, generated by the velocity
function
generator,
to
be
passed
into
the
summing
junction
of
the
summing
amplifier
U16.
S.3.2.2 Mode Control
The Mode Control
circuitry
is shown on Schematic No. 102810, sheet 1. When Track Offset
Plus (NLTOPG)
at
pin
26
of
J201
(zone E19)
is
low
and Track
Offset
Minus
(NLTOMG) at
pin
2S
of
J201
is
high,
transistor
as
is
off
and
06
is
on; consequently,
the
signal at
TP11
will
be +
4.S
± 1.0v. Conversely, a
high
state
of
NLTOPG and a
low
state
of
NL TOMG turns
as on and turns
06
off,
and
the
voltage
at
TP11
will
be
-4.Sv
± 1.0v. When NLTOPG and
NLTOMG both are high,
transistors
as and
06
are both on and
the
voltage at
TP11
will
beOv.
Forward
Slow
Mode (NLFSM1)
low
at pin 24
of
J201, Reverse
Slow
Mode (NLRSM1) high
at pin
23
of
J201
and
the
high
output
of
U10-A pin 4 (I.e., Heads Retracted (SHRXG)
low
at
TP14, zone
011) causes
07
and
010
(zone C16)
to
turn
off,
and as (zone C17)
to
turn on.
Thus, the signal at
TP10
will
be
+4.Sv
±1.0v.
Conversely, when NLFSM1 is high,
5-4
i
..
. i
.j
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