NLRSM1
is low and SHRXG is low,
Q8
and
Q10
are turned
off
and
Q7
is turned on.
Consequently, the signal at
TP10
is
-4.5v
± 1.0v. When NLFSM1 is high,
NLRSM1
is low
and
SHRXG is high,
Q8
is turned off. However,
Q10
and
Q7
are turned on and the signal at
TP10
is approximately 0.3v. Finally, when NLFSM1 and NLRSM1 are high,
Q7
and
Q8
are
turned on, and regardless of the state of
SHRXG, the voltage at
TP10
is
Ov.
Potentiometer
R22
(zone
F16)
is used to adjust for the dc offsets when the servo is
in
the
Position Mode.
TP19
and
R40
(zone 015) provide a means
to
introduce
an
external
perturbation signal into the summing amplifier.
5.3.2.3 Position Transducer
Signal Conditioners
The Position Transducer
Signal Conditioner circuitry is shown on Schematic
No.1
0281
0,
sheet 1. These circuits are employed
to
amplify the low level position transducer signals
(X
+
0,
X + 90, Index, Heads Retracted) and convert them
to
appropriate logic signals
(SPRCG, SPQCG, SPTIG, and SHRXG). J203 (zone A15) connects all position transducer
signals and velocity transducer signals to the
Servo PCBA. Outputs from the Position
Transducer
Signal Conditioners are routed to the Logic PCBA via edge connector J202
(zone B11).
Figure
5-2
describes the position transducer output signals, namely Heads Retracted,
Index, X + 0 and X +
90,
at pins
6,
1,
3,
and
2,
respectively,
of
connector J203,
as
the
positioner carriage is moved in the forward direction, i.e., toward the spindle. The
amplitude
of
the Heads Retracted and Index signal is approximately 10 mv at pins 6 and 1
of J203, respectively. The amplitude
of
X + 0 and X +
90
signal is approximately 120 mv
to
200
mv, at pins 3 and 2
of
J203, respectively.
The output
of
the Heads Retracted, Index, X +
0,
and X +
90
amplifiers can
be
monitored
at TP6,
TP3,
TP20, and TP2, respectively. Figure
5-3
describes the output of these
amplifiers and should
be
referenced in conjunction with Figure 5-2.
Potentiometers
R70
(zone F14),
R79
(zone
E14),
R98
(zone
C14)
provide dc bias for balance
adjustments of the X
+
0,
and X +
90
and Index signals, respectively.
R69
(zone
F13)
provides gain adjustments for
(X
+
0)
signal at TP20.
R226
(zone
E14)
provides gain
adjustments
for
(X
+
90)
signal at
TP2.
Type
741
operational amplifiers
(U1,
U2, U6,
and
U7)
are used as high gain inverting amplifiers to amplify these signals.
When
R69
(the X + 0 gai n potentiometer) and
R70
(the balance potentiometer) are properly
adjusted, the output at
TP20
should
be
12v peak-to-peak. The X + 0 amplifier output at
TP2
should
be
between
6v
peak-to-peak and 12v peak-to-peak. The change
in
transition
(from positive to negative and vice versa) at
TP6
and
TP3
should
be
from +
7v
+
5v
to
-7v
+
5v
and vice versa when
R98,
the Index balance potentiometer, is properly adjusted.
The
amplified Heads Retracted, Index, X +
0,
X +
90
(see Figure 5-2) are then converted
into their corresponding logic signals shown in Figure 5-3, namely Heads Retracted
(SHRXG), Position Transducer
Index (SPTIG), Position Reference Clock (SPRCG), and
Position Quadrature
Clock (SPQCG). These logic signals
can
be
monitored
at
TP14,
TP7,
TP8,
and
TP13,
respectively. Type
75107
dual line receivers (U11-A, U11-B, U10-A, U10-B)
are used in the circuit
as
comparators for analog-to-digital conversion.
The
R-C
network
in
the feedback loop around comparators U11-A, U11-B, and U10-A,
U10-B provides
ac
and dc hysteresis.
An
example of
this
network is
C5,
R76,
Rn,
and
R85
in
the feedback path of U11-B (zone 013). These networks assure a single transition
crossover detection of the analog input signals and provide good dc noise margins for
analog inputs
to
the comparators.
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