Status Reporting System R&S SMB
1407.0806.32 5.24 E-2
Status Byte (STB) and Service Request Enable Register (SRE)
The STB is already defined in IEEE 488.2. It provides a rough overview of the instrument status by
collecting the pieces of information of the lower registers A special feature is that bit 6 acts as the sum
bit of the remaining bits of the status byte.
The STATUS BYTE is read out using the command "*STB?" or a serial poll.
The STB is linked to the SRE.Each bit of the STB is assigned a bit in the SRE. Bit 6 of the SRE is
ignored. If a bit is set in the SRE and the associated bit in the STB changes from 0 to 1, a Service
Request (SRQ) is generated on the IEC/IEEE bus or via the Ethernet, which triggers an interrupt in the
controller if this is appropriately configured and can be further processed there.
The SRE can be set using command "*SRE" and read using "*SRE?".
Meaning of the bits used in the status byte
Bit no. Meaning
0...1
Not used
2 Error Queue not empty
The bit is set when an entry is made in the error queue.
If this bit is enabled by the SRE, each entry of the error queue generates a Service Request. Thus an error can
be recognized and specified in greater detail by polling the error queue. The poll provides an informative error
message. This procedure is to be recommended since it considerably reduces the problems involved with
Remote control.
3
Not used
4 MAV bit (Message available)
The bit is set if a message is available in the output buffer which can be read.
This bit can be used to enable data to be automatically read from the instrument to the controller.
5 ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set and enabled in the
event status enable register.
Setting of this bit indicates a serious error which can be specified in greater detail by polling the event status
register.
6 MSS bit (Master-Status-Summary-Bit)
The bit is set if the instrument triggers a service request. This is the case if one of the other bits of this register is
set together with its mask bit in the service request enable register SRE.
7
Not used
IST-Flag and Parallel Poll Enable Register (PPE)
By analogy with the SRQ, the IST flag combines the entire status information in a single bit. It can be
queried by means of a parallel poll (cf. Section "Parallel Poll") or using the command "*IST?".
The parallel poll enable register (PPE) determines which bits of the STB contribute to the IST flag. The
bits of the STB are ANDed with the corresponding bits of the PPE, with bit 6 being used as well in
contrast to the SRE. The IST flag results from the ORing of all results. The PPE can be set using
commands "*PRE" and read using command "*PRE?".
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