ST STM32H7 Series User Manual

The STM32 Cortex-M4 instruction set PM0214
112/262 PM0214 Rev 9
; top 32 bits to R6, and the bottom 32 bits to R3
UMLAL R2, R1, R3, R5 ; Multiplies R5 and R3, adds R1:R2, writes to R1:R2.
3.6.3 SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax
op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
Where
• op is one of the following:
SMLA: Signed multiply accumulate long (halfwords). X and Y specifies which half of the
source registers Rn and Rm are used as the first and second multiply operand.
– If X is B, then the bottom halfword, bits [15:0], of Rn is used.
– If X is T, then the top halfword, bits [31:16], of Rn is used.
– If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
– If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMLAW: Signed multiply accumulate (word by halfword). Y specifies which half of the
source
Rm register is used as the second multiply operand.
– If Y is T, then the top halfword, bits [31:16] of Rm is used.
– If Y is B, then the bottom halfword, bits [15:0] of Rm is used.
• ‘cond’ is an optional condition code (see Conditional execution on page 65)
• ‘Rd’ is the destination register. If Rd is omitted, the destination register is Rn.
• ‘Rn’, ‘Rm’ are registers holding the values to be multiplied.
• ‘Ra’ is a register holding the value to be added to or subtracted from.
Operation
The SMALBB, SMLABT, SMLATB, SMLATT instructions:
1. Multiply the specified signed halfword, top or bottom, values from Rn and Rm.
2. Add the value in Ra to the resulting 32-bit product.
3. Write the result of the multiplication and addition in Rd.
4. The non-specified halfwords of the source registers are ignored.
The SMLAWB and SMLAWT instructions:
1. Multiply the 32-bit signed values in Rn with:
a) The top signed halfword of Rm, T instruction suffix.
b) The bottom signed halfword of Rm, B instruction suffix.
2. Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product.
3. Write the result of the multiplication and addition in Rd.
4. The bottom 16 bits of the 48-bit product are ignored.
5. If overflow occurs during the addition of the accumulate value, the instruction sets the
Q flag in the APSR. No overflow can occur during the multiplication.
Restrictions
In these instructions, do not use SP or PC.

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English

Summary

About this document

Typographical Conventions

Defines formatting used in the document for clarity.

List of Abbreviations for Registers

Provides a list of abbreviations used in register descriptions for quick reference.

STM32 Cortex-M4 Processor Overview

Introduces the STM32 Cortex-M4 processor's architecture and key features.

The Cortex-M4 Processor

Programmer's Model

Describes registers, modes, and privilege levels for software execution.

Memory Model

Details the processor's memory map, access behavior, and bit-banding features.

Exception Model

Explains exception states, types, priorities, and handling mechanisms.

Fault Handling

Covers fault types, escalation, status registers, and lockup conditions.

Power Management

Describes mechanisms for entering and exiting low-power sleep modes.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary

Lists supported Cortex-M4 instructions and their organization.

Memory Access Instructions

Details instructions for loading and storing data from/to memory.

General Data Processing Instructions

Explains instructions for arithmetic, logical, and data manipulation.

Multiply and Divide Instructions

Describes instructions for multiplication and division operations.

Floating-Point Instructions

Details instructions for FPU operations, including VFPv4-SP extension.

Miscellaneous Instructions

Covers instructions like breakpoints, barriers, and supervisor calls.

Core Peripherals

About the STM32 Cortex-M4 Core Peripherals

Introduces the core peripherals accessible via the Private Peripheral Bus (PPB).

Memory Protection Unit (MPU)

Explains the MPU for memory region definition and access control.

Nested Vectored Interrupt Controller (NVIC)

Describes the NVIC for managing interrupts and exceptions with priority levels.

System Control Block (SCB)

Details registers for system control, configuration, and exception reporting.

SysTick Timer (STK)

Explains the 24-bit SysTick timer for system timing and RTOS ticks.

Floating Point Unit (FPU)

Describes the FPU for single-precision floating-point operations.

Revision History